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This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

from_list

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),


getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

target

to_list

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),


getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required maximum delay value in ns for specified paths.

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.setMaxDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', delay = 3.9)
project.setMaxDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)         
project.setMaxDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 4.0) 
project.setMaxDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)  
project.setMaxDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

...

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

from_list

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),


getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

to_list

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),


getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required minimum delay value in ns for specified paths.

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.addMinDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', 1.2)
project.addMinDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getPorts("cpt_in[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)

...

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

from_list

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),


getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

target

to_list

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),


getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required minimum delay value in ns for specified paths.

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.setMinDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', target = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', delay = 1.2)
project.setMinDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

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