...
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.addMulticyclePath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', 'getRegister('UUT2\|dout_reg[61]')', 2)
project.addMulticyclePath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 2) |
| Note |
|---|
This method is only available for path(s) whose source and target registers are clocked by the same clock! |
setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')
...
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.setMulticyclePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', pathMultiplier = 2)
project.setMulticyclePath(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', pathMultiplier = 2) |
| Note |
|---|
This method is only available for path(s) whose source and target registers are clocked by the same clock! |
addFalsePath(from_list, to_list)
...