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Name | Type | Description |
target | string | Specifies how to get a clock related point. A valid argument can be: |
name | string | User clock name of the created clock. |
period | float | The period value. |
rising | float | Specifies the rising edge for clock waveform. Range [0, period[ (the default value is 0) |
falling | float | Specifies the falling edge for clock waveform. Range ]rising, rising + period] (default value is period/2) |
...
Name | Type | Description |
target | string | Mandatory. The argument that specifies how to get a clock related point. A valid argument can be: |
name | string | Optional. User clock name of the created clock, default name is target_str |
period | float | Mandatory. Period for the clock waveform. Must be positive, default value is period/2 |
rising | float | Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0. |
falling | float | Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2. |
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Name | Type | Description |
source | string | Specifies how to get a source clock related point. A valid argument can be: |
target | string | Specifies how to get a clock related point. A valid argument can be: |
name | string | User clock name of the generated clock |
relationship | dictionary | The relationship for computing clock wave of the generated clock from the master clock. A valid parameter can be: MultiplyBy : unsigned DivideBy : unsigned DutyCycle : unsigned (1 to 99) Phase : unsigned (0 to 359) Offset : integer (delay in ns) Edges : list [unsigned, unsigned, unsigned] (in non-decreasing order) EdgeShift : list [integer, integer, integer] (delay in ns) |
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Name | Type | Description |
source | string | Mandatory. Specifies how to get source clock related point. A valid argument can be: |
target | string | Mandatory. Specifies how to get a clock related point. A valid argument can be: |
name | string | User clock name of the generated clock |
...
Name | Type | Description |
group1_list | string | Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: |
group2_list | string | Same as the argument "group1_list" |
option | string | A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time. |
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Name | Type | Description |
group1 | string | Mandatory. Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: |
group2_list | string | Mandatory. Same as the argument "group1_list" |
option | string | Mandatory. A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time |
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Name | Type | Description |
from_list | string | Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
to_list | string | Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | float | The required maximum delay value in ns for specified paths. |
...
Name | Type | Description |
source | string | Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
target | string | Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | float | The required maximum delay value in ns for specified paths. |
...
Name | Type | Description |
from_list | string | Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
to_list | string | Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | float | The required minimum delay value in ns for specified paths. |
...
Name | Type | Description |
source | string | Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: |
target | string | Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: |
delay | float | The required minimum delay value in ns for specified paths. |
...
Name | Type | Description |
from_list | string | Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: |
to_list | string | Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: |
cycle_count | unsigned | An unsigned value that represents a number of cycles the data path must have for setup check. |
...
Name | Type | Description |
source | string | Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: |
target | string | Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: |
pathMultiplier | integer | Mandatory. A value that represents a number of cycles. Must be greater than 1. |
...
Name | Type | Description |
from_list | string | Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: |
to_list | string | Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: |
Examples:
| Code Block | ||||
|---|---|---|---|---|
| ||||
project = createProject()
project.load('routed.nym')
project.addFalsePath('getRegister('UUT1\|Gen_seq[3].seq_i|temp_reg[1]')','getRegister('UUT2\|dout_reg[61]')')
project.addFalsePath('getRegistersByClock(clk1)','getRegistersByClock(clk2)')
project.addFalsePath('getRegister(cpt_in_p_reg[0])','')
project.addFalsePath('getPort(cpt_in[0])','getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.addFalsePath('getPorts("cpt_in[`[0-3]`]")', 'getRegistersByClock(clk2)')
project.addFalsePath('getRegistersByClock(clk1)', 'getWFGOutput(i_WFG_0)') |
...
Name | Type | Description |
source | string | Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: |
target | string | Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: |
Examples:
| Code Block | ||||
|---|---|---|---|---|
| ||||
project = createProject()
project.load('routed.nym')
project.setFalsePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegister(cpt_in_p_reg[0])')
project.setFalsePath(source = 'getPort(cpt_in[0])', target = 'getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.setFalsePath(source = 'getPorts("cpt_in[`[0-3]`]")', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getWFGOutput(i_WFG_0)') |
...
Name | Type | Description |
clock | string | Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is |
clock_mode | string | Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". |
minimum_delay | float | Applies value as minimum data arrival time. |
maximum_delay | float | Applies value as maximum data arrival time. |
port_list | string | Specifies how to get a list of input pads. A valid argument can be: |
Examples:
| Code Block |
|---|
project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setInputDelay(getClock('CLK'),'rise', 1, 1.5, getPort('RST')) |
...
Name | Type | Description |
clock | string | Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is |
clockMode | string | Optional. Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". Default value is rise. |
min | float | Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
max | float | Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0. |
ports | string | Mandatory. Specifies how to get a list of input pads. A valid argument can be: |
Examples:
| Code Block |
|---|
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name = 'clock',period = 8)
project.setInputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
...
Name | Type | Description |
clock | string | Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: |
clock_mode | string | Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". |
minimum_delay | integer | Applies value as minimum data arrival time. |
maximum_delay | integer | Applies value as maximum data arrival time. |
port_list | string | Specifies how to get a list of output pads. A valid argument can be: |
Examples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setOutputDelay(getClock('CLK'),'rise', 1.0, 1.5, getPorts('dataout[`[0−5]`]')) |
...
Name | Type | Description |
clock | string | Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: |
clockMode | string | Optional. Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". The default value is “rise”. |
min | float | Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
max | float | Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0. |
ports | string | Mandatory. Specifies how to get a list of input pads. A valid argument can be: |
Examples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet('CLK')', name = 'CLK', period = 8)
project.setOutputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
...
Name | Type | Description |
value | unsigned | The valid constant. Values can be 0 or 1 |
net_list | string | Specifies how to get one or several nets. A valid argument can be |
Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered. The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.
...
Name | Type | Description |
|---|---|---|
value | unsigned | The valid constant. Values can be 0 or 1 |
netList | string | Specifies how to get one or several nets. A valid argument can be: |
Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered. The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.
...