...
| Note |
|---|
The name of the clock net is case sensitive |
ExampleExamples:
...
In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :
...
Name | Type | Description |
target | string | Mandatory. The query which specifies how to get a clock related point. A valid query can be: getPort(port_name), getRegisterClock(register_name) or getRegister(register_name), getClockNet(clock_net_name). |
name | string | Optional. User clock name of the created clock, default name is target_str |
period | float | Mandatory. Period for the clock waveform. Must be positive, default value is period/2 |
rising | float | Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0. |
falling | float | Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2. |
ExampleExamples:
...
In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :
...
| Note |
|---|
Frequency-based and edge-based relationships are mutually exclusive. |
ExampleExamples:
...
In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:
...
| Note |
|---|
Frequency-based and edge-based relationships are mutually exclusive. |
ExampleExamples:
...
In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:
...
Name | Type | Description |
group1_list | string | The argument which specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name) and getClocks(name_expression). |
group2_list | string | Same as the argument "group1_list" |
option | string | A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.createClock('getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])', 'clk1', 2.7)
project.createClock('getClockNet(CLOCK[2])', 'clk2', 5, 0, 2)
project.setClockGroup('getClock(clk1)', 'getClock(clk2)', 'exclusive') |
...
Name | Type | Description |
group1 | string | Mandatory. The argument which specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name) and getClocks(name_expression). |
group2_list | string | Mandatory. Same as the argument "group1_list" |
option | string | Mandatory. A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.createClock(name ='clk1', period = 2.7, target= 'getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])')
project.createClock(name = 'clk2', period = 5, rising = 0, falling = 2, target= 'getClockNet(CLOCK[2])')
project.setClockGroup(group1 = 'getClock(clk1)', group2 = 'getClock(clk2)', option = 'exclusive') |
...
Name | Type | Description |
from_list | string | The argument which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
to_list | string | The argument which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
delay | float | The required maximum delay value in ns for specified paths. |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.addMaxDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', 'getRegister('UUT2\|dout_reg[61]')', 3.9)
project.addMaxDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 4.0)
project.addMaxDelayPath('getPorts("cpt_in[`[1-3]`]")','getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMaxDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0) |
...
Name | Type | Description |
source | string | The argument which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
target | string | The argument which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
delay | float | The required maximum delay value in ns for specified paths. |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.setMaxDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', delay = 3.9)
project.setMaxDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMaxDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 4.0)
project.setMaxDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMaxDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0) |
...
Name | Type | Description |
from_list | string | The argument which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
to_list | string | The argument which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
delay | float | The required minimum delay value in ns for specified paths. |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.addMinDelayPath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', 1.2)
project.addMinDelayPath('getPort(cpt_in[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegister(i_cpt_0\|s_cpt_out_reg[0])', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getPorts("cpt_in[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0)
project.addMinDelayPath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 8.0) |
...
Name | Type | Description |
source | string | The argument which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
target | string | The argument which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), |
delay | float | The required minimum delay value in ns for specified paths. |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.setMinDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', target = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', delay = 1.2)
project.setMinDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0) |
...
Name | Type | Description |
from_list | string | The argument which specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name). |
to_list | string | The argument which specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name). |
cycle_count | unsigned | An unsigned value that represents a number of cycles the data path must have for setup check. |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.addMulticyclePath('getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', 'getRegister('UUT2\|dout_reg[61]')', 2)
project.addMulticyclePath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 2) |
...
Name | Type | Description |
source | string | Mandatory. The argument which specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name). |
target | string | Mandatory. The argument which specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name). |
pathMultiplier | integer | Mandatory. A value that represents a number of cycles. Must be greater than 1. |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.setMulticyclePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', pathMultiplier = 2)
project.setMulticyclePath(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', pathMultiplier = 2) |
...
Name | Type | Description |
from_list | string | The argument which specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name) |
to_list | string | The argument which specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name) |
ExampleExamples:
| Code Block | ||||
|---|---|---|---|---|
| ||||
project = createProject()
project.load('routed.nym')
project.addFalsePath('getRegister('UUT1\|Gen_seq[3].seq_i|temp_reg[1]')','getRegister('UUT2\|dout_reg[61]')')
project.addFalsePath('getRegistersByClock(clk1)','getRegistersByClock(clk2)')
project.addFalsePath('getRegister(cpt_in_p_reg[0])','')
project.addFalsePath('getPort(cpt_in[0])','getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.addFalsePath('getPorts("cpt_in[`[0-3]`]")', 'getRegistersByClock(clk2)')
project.addFalsePath('getRegistersByClock(clk1)', 'getWFGOutput(i_WFG_0)') |
...
Name | Type | Description |
source | string | Mandatory. The argument which specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name) |
target | string | Mandatory. The argument which specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name) |
ExampleExamples:
| Code Block | ||||
|---|---|---|---|---|
| ||||
project = createProject()
project.load('routed.nym')
project.setFalsePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegister(cpt_in_p_reg[0])')
project.setFalsePath(source = 'getPort(cpt_in[0])', target = 'getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.setFalsePath(source = 'getPorts("cpt_in[`[0-3]`]")', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getWFGOutput(i_WFG_0)') |
...
Name | Type | Description |
clock | string | The argument which specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is getClock(clock_name). |
clock_mode | string | Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". |
minimum_delay | float | Applies value as minimum data arrival time. |
maximum_delay | float | Applies value as maximum data arrival time. |
port_list | string | The argument which specifies how to get a list of input pads. A valid argument can be: getPort(port_name), getPorts(name_expression). |
ExampleExamples:
| Code Block |
|---|
project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setInputDelay(getClock('CLK'),'rise', 1, 1.5, getPort('RST')) |
...
Name | Type | Description |
clock | string | Mandatory. The argument which specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is getClock(clock_name). |
clockMode | string | Optional. Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". Default value is rise. |
min | float | Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
max | float | Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0. |
ports | string | Mandatory. The argument which specifies how to get a list of input pads. A valid argument can be: getPort(port_name), getPorts(name_expression). |
ExampleExamples:
| Code Block |
|---|
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name = 'clock',period = 8)
project.setInputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
...
Name | Type | Description |
clock | string | The argument which specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name). |
clock_mode | string | Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". |
minimum_delay | integer | Applies value as minimum data arrival time. |
maximum_delay | integer | Applies value as maximum data arrival time. |
port_list | string | The argument which specifies how to get a list of output pads. A valid argument can be: getPort(port_name), getPorts(name_expression). |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'),'CLK',8)
project.setOutputDelay(getClock('CLK'),'rise', 1.0, 1.5, getPorts('dataout[`[0−5]`]')) |
...
Name | Type | Description |
clock | string | Mandatory. The argument which specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name). |
clockMode | string | Optional. Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". The default value is “rise”. |
min | float | Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
max | float | Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0. |
ports | string | Mandatory. The argument which specifies how to get a list of input pads. A valid argument can be: getPort(port_name), getPorts(name_expression). |
ExampleExamples:
| Code Block | ||
|---|---|---|
| ||
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet('CLK')', name = 'CLK', period = 8)
project.setOutputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)') |
...
developCKGs() allows the user to create generated clocks for CKGs output pins. For example, before activating a generated clock which is based on a clock driven by a WFG, user needs to launch this method for generating the base clock. Without this method, nxmap automatically derives a clock on each output of the CKGs after activating all of the given timing constraints.
ExampleExamples:
| Code Block | ||||
|---|---|---|---|---|
| ||||
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
project.developCKGs()
project.createGeneratedClock(source = 'getWFGOutput(wfg_clk[1])', target= 'getRegister(data_reg[0])', name='clk1_div2', divideBy = 2) |
...