...
set_input_delay [-clock clock_name]
[-clock_fall string ]
[-max float]
[-min float]
<delay>
...
Name | Description | ||
---|---|---|---|
clock | Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. | ||
clock_fall | Specifies that input delay is relative to the falling or edge of the clock. When it is not set, the delay is applied on the rising edge of the clock. It must be "rise"' or "fall". | ||
max | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. | ||
min | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. | ||
delay | Specifies the arrival time in nanoseconds or picoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge. | ||
ports | Provides a list of input ports in the current design to which | ||
|
Examples:
Code Block |
---|
create_clock -period 10 -name "CLK_MAIN" [get_ports clk]
set_input_delay -clock [get_clocks CLK_MAIN] -max 1.0 [get_ports {cpt_in[0]}]
set_input_delay -clock [get_clocks CLK_MAIN] -clock_fall -min 4.0 [get_ports {cpt_in[2]}] |
If cpt_in is a bus of 4 bits, the constraint should be written as below :
Code Block |
---|
set_input_delay -clock [get_clocks CLK_MAIN] -clock_fall -min 4.0 [get_ports {cpt_in*}] |
set_output_delay
Constrains output and in/out (bidirectional) ports, port busses, and pins (that are valid start points) within the design relative to a clock edge. If you omit both the -min
and -max
options, the delay is assumed to apply for both setup and hold analysis.
set_output_delay [-clock clock_name]
[-clock_fall ]
[-max float]
[-min float]
<delay>
<ports>
Arguments:
Name | Description |
---|---|
clock | Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. |
clock_fall | Specifies that input delay is relative to the falling edge of the clock. When it is not set, the delay is applied on the rising edge of the clock. |
max | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
min | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. |
delay | Specifies the arrival time in nanoseconds or picoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge. |
ports | Provides a list of |
output ports in the current design to which | |||
|
Examples:
Code Block |
---|
create_clock -period 10 -name "CLK_MAIN" [get_ports clk]
set_output_delay -clock [get_clocks CLK_MAIN] -max 1.0 [get_ports {cpt_out[0]}]
set_output_delay -clock [get_clocks CLK_MAIN] -clock_fall -min 4.0 [get_ports {cpt_out[2]}] |
If cpt_out
is a bus of 4 bits, the constraint should be written as below :
Code Block |
---|
set_output_delay -clock [get_clocks CLK_MAIN] -clock_fall -min 4.0 [get_ports {cpt_out*}] |
set_min_delay
Constrains the specified timing paths by the given delay value for hold analysis.
set_min_delay [-from string]
[-to string]
<delay>
Arguments:
Name | Description | ||
---|---|---|---|
from | The argument which specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: | ||
to | The argument which specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: | ||
delay | The required minimum delay value in ns for specified paths. | ||
|
Examples:
Code Block |
---|
set_min_delay -from [get_registers {i_cpt_0|s_cpt_out_reg[0]}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 8000
set_min_delay -from [get_ports {cpt_in[0]}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 2000
set_min_delay -from [get_ports {cpt_in*}] -to [get_registers {i_cpt_1|s_cpt_out_reg[1]}] 1000 |