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-from and -to options apply the constraint to both the rising and falling edges
Examples:
| Code Block |
|---|
set_fasefalse_path -from [get_ports cpt_in*] -to [get_clocks clk2] set_false_path -from [get_registers {cpt_in_p_reg[0]}] -to [get_registers {i_cpt_0|s_cpt_out_reg[0]}] set_false_path -from [get_ports {cpt_in[0]}] -to [get_registers {cpt_in_p_reg[0]}] |
set_input_delay
Constrains input and in/out (bidirectional) ports, port busses, and pins (that are valid start points) within the design relative to a clock edge. If you omit both the -min and -max options, the delay is assumed to apply for both setup and hold analysis.
set_input_delay [-clock clock_name]
[-clock_fall string]
[-max float]
[-min float]
<delay>
<ports>
Arguments:
Name | Description | ||
|---|---|---|---|
clock | Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. | ||
clock_fall | Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". | ||
max | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. | ||
min | Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0. | ||
delay | Specifies the arrival time in nanoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge. | ||
ports | Provides a list of input ports in the current design to which | ||
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Examples: