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project = createProject()
project.load('routed.nym')
project.addMulticyclePath('getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]')', 'getRegister('UUT2|dout_reg[61]')', 2)
project.addMulticyclePath('getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', 2) |
createClock( )
/ ! \ DEPRECATED / ! \ Please use createClock(target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period]) instead.
This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings are in ns or ps.
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createGeneratedClock(source, target, name, relationship)
This method is used to create an internal generated / ! \ DEPRECATED / ! \ Please use createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value) instead.
This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.
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The diagram of the above command would be:
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createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)
This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
source | string | Mandatory. The command which specifies how to get source clock related point. A valid command can be: getClock(), getPort(port_name), getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name), getWFGOutput(wfg_name) |
target | string | Mandatory. The command which specifies how to get a clock related point. A valid command can be: getRegisterClock(register_name), getRegister(register_name)), getClockNet(clock_net_name) |
name | string | User clock name of the generated clock |
Parameters for computing clock wave of generated clock from master clock can be:
Key | Type | Description and value |
multiplyBy | int | Period multiplication factor. The value must be greater or equal to 1. Default value is 1 |
divideBy | int | Period division factor. The value must be greater or equal to 1. Default value is 1 |
dutyCycle | int | Duty cycle of clock period. The range must be from 1 to 99. Default value is 50.0 |
phase | unsigned | The range must be from 0 to 359 |
invert | boolean | Invert the clock signal (~ phase = 180) |
offset | float | Offset for rising edge |
edges | int list | Specifies the edges of the master clock to use in defining transitions on the generated clock. List in non-decreasing order. Mutually exclusive with 'multiplyBy' or 'divideBy' |
edgeShift | float list | Shifts the edges of the generated clock by the specified values relative to the master clock. Mutually exclusive with 'multiplyBy' or 'divideBy' |
| Note |
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Frequency-based and edge-based relationships are mutually exclusive. |
Example:
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In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:
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project = createProject()
project.load('routed.nym')
project.createClock(source = 'getPort(Clk)', name = 'Clk', period = 10)
project.createGeneratedClock(source = 'getRegisterClock(clk_reg)', target = 'getRegisterClock(reg2)', name = 'clk1', divideBy = 2)
or
project.createGeneratedClock(source = 'getClock(Clk)', target = getRegisterClock(reg2)', name = 'clk1', edges = [2, 4, 6]) |
| Note |
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The following script is incorrect in this case: ########### INCORRECT SCRIPT ##########
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The diagram of the above command would be:
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developCKGs()
This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project. This constraint is used by timing driven algorithms and static timing analysis.
This method takes no argument.
developCKGs() allows the user to create generated clocks for CKGs output pins. For example, before activating a generated clock which is based on a clock driven by a WFG, user needs to launch this method for generating the base clock.
Without this method, nxmap automatically derives a clock on each output of the CKGs after activating all of the given timing constraints.
Example:
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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
project.developCKGs()
project.createGeneratedClock(source = 'getWFGOutput(wfg_clk[1])', target= 'getRegister(data_reg[0])', name='clk1_div2', divideBy = 2) |
setAnalysisConditions(conditions)
/ ! \ DEPRECATED / ! \ Please use setAnalysisConditions(conditions = 'conditions') instead.
This method is used to specify the chip conditions for static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
conditions | string | the command which specifies the conditions for static timing analysis. |
Example:
| Code Block |
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project.setAnalysisConditions(WorstCase) |
setAnalysisConditions(conditions = 'conditions')
This method is used to specify the chip conditions for the static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
conditions | string | the command which specifies the conditions for static timing analysis. |
Example:
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project.setAnalysisConditions(conditions = 'worstcase') |
setCaseAnalysis(value, net_list)
/ ! \ DEPRECATED / ! \ Please use setCaseAnalysis(value = ‘value', netList = 'netList’) instead.
This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
value | unsigned | The valid constant. Values can be 0 or 1 |
net_list | string | The command which specifies how to get one or several nets. A valid command can be getNet(net_name), getNets(net_name_expression), getPort(port_name), getPorts(port_name_expression) |
Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered.
The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.
Example:
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In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer, but only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).
| Code Block | ||
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project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(1, 'getNet(sel)') |
setCaseAnalysis(value = ‘value', netList = 'netList’)
This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.
Arguments:
Name | Type | Description |
|---|---|---|
value | unsigned | The valid constant. Values can be 0 or 1 |
netList | string | The command which specifies how to get one or several nets. A valid command can be: getNet(net_name), getNets(net_name_expression), getPort(port_name), getPorts(port_name_expression |
Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered.
The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.
Example:
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In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer, but only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).
| Code Block | ||
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project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(value = '1', netList = 'getNet(sel)') |
setClockGroup(group1_list, group2_list, option)
/ ! \ DEPRECATED / ! \ Please use setClockGroup(group1 = ‘group1’, group2 = ‘group2', option = 'option’) instead.
This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis.
A clock cannot be in a different group from itself.
Arguments:
Name | Type | Description |
group1_list | string | The argument which specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name) and getClocks(name_expression). |
group2_list | string | same as the argument "group1_list" |
option | string | a valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time |
Example:
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project = createProject()
project.load('routed.nym')
project.createClock('getRegister(UUT1|Gen_seq[2].seq_i|temp_reg[13])', 'clk1', 2.7)
project.createClock('getClockNet(CLOCK[2])', 'clk2', 5, 0, 2)
project.setClockGroup('getClock(clk1)', 'getClock(clk2)', 'exclusive') |
setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)
This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis.
A clock cannot be in a different group from itself.
Arguments:
Name | Type | Description |
group1 | string | Mandatory. The argument which specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name) and getClocks(name_expression). |
group2_list | string | Mandatory. Same as the argument "group1_list" |
option | string | Mandatory. A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time |
Example:
| Code Block | ||
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project = createProject()
project.load('routed.nym')
project.createClock(name ='clk1', period = 2.7, target= 'getRegister(UUT1|Gen_seq[2].seq_i|temp_reg[13])')
project.createClock(name = 'clk2', period = 5, rising = 0, falling = 2, target= 'getClockNet(CLOCK[2])')
project.setClockGroup(group1 = 'getClock(clk1)', group2 = 'getClock(clk2)', option = 'exclusive') |