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It is recommended to rather use python method addMemoryInitialization described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481 as it is compliant with inferred and instantiated memories.
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In order to get complexity module by module without confining it in a region, it is possible to use addModule method described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481.
Refer to #Floor_planning_Complexity for more details.
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Please refer to createClock and createGeneratedClock described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481.
If a PLL is used, PLL output clock frequencies are automatically computed by the software.
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Please refer to addFalsePath and addMultiCyclePath in Nxmap user manual /wiki/spaces/~814749387/pages/48660481.
Clock groups can be created if clock domains are completely unrelated.
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It is possible to map this operators in LUT, Carry or DSP thanks to addMappingDirective method described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481.
By default, adders are mapped into Carry and Multipliers in DSP. But it can sometimes be interesting to change default mapping directives.
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Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction thanks to addMappingDirective method described in Nxmap user manual. /wiki/spaces/~814749387/pages/48660481.
By default, small memories (equal or less than 64x16) will be mapped into RF and bigger mapped into RAM. But it can sometimes be interesting to change default mapping directives.
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Define a floor plan for the design depending on module relationships and pinout.
Apply the floor plan to your NXmap project using confineModule described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481. Check #Floor_planning_Constrain_module for information about constraint setting.
If needed, repeat this process going deeper and deeper in the design hierarchy.
For last most critical paths, use constrainPath described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481in order to create a region with only a few elements contained into the specified path. Check #Floor_planning_Constrain_path_between_registers for information about constraint setting.
It can also have a very positive impact to create unitary projects and reuse the routed projects as a blackbox in your final top project using addBlackBox described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481.
It is also possible to place manually instances in a specified spot thanks to the following NXpython methods all described in Nxmap user manual /wiki/spaces/~814749387/pages/48660481:
addPLLLocation for PLL instance in a CKG. Check #Instance_placing_Ring_placing for information about constraint setting.
addWFGLocation for WFG instance in a CKG and a WFG spot. Check #Instance_placing_Ring_placing for information about constraint setting.
addRAMLocation for RAM instance in a CGB. Check #Instance_placing_Ram_placing for information about constraint setting.
addDSPLocation for DSP instance in a CGB and a DSP spot. Check #Instance_placing_Dsp_placing for information about constraint setting.
setSite for LUT/DFF/CY in a TILE. Check #Instance_placing_Tile_placing for information about constraint setting.
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Please have a look at Training Package Application Note StaConstraint/GeneratedClock project.
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In order to declare a path between 2 registers as a false path, multi-cycle path, min or max delay path, clock in your project in order to get required frequencies in logs, follow the following steps:
Launch your design for the first time without constraint.
Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.
Add the constraint specifying area coordinates, for instance “p.addFalsePath('getRegisters(module0|submodule0|pipe_reg[0])','getRegisters(module0|submodule0|pipe_reg[0])')”, and relaunch the project.
Check in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timingt report the path no longer appears.
Please have a look at Training Package Application Note StaConstraint/FalsePath project.
How to improve STA results
STA tool
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Grab the clock name getting the hierarchy path to the generated clock.
Add the constraint specifying clock parameters, for instance “p.createGeneratedClock(getClock('clk_main'),getRegisterClock('i_clock_0|counter_reg[0]'), 'clk_fabric',{'DivideBy': 2})”.
Check timing files are created for this new clock domain.
Please have a look at Training Package Application Note StaConstraint/GeneratedClock project.
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In order to declare a path between 2 registers as a false path, multi-cycle path, min or max delay path, follow the following steps:
Launch your design for the first time without constraint.
Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.
Add the constraint specifying area coordinates, for instance “p.addFalsePath('getRegisters(module0|submodule0|pipe_reg[0])','getRegisters(module0|submodule0|pipe_reg[0])')”, and relaunch the project.
Check in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timingt report the path no longer appears.
Please have a look at Training Package Application Note StaConstraint/FalsePath project.
How to improve STA results
STA tool
It is recommended to launch the STA tool after Placing 1/5 step named “Preparing”. It allows to witness the number of logic elements crossed and check if it is possible to reach performances when the margin in the most optimistic scenario is high enough.
ClockCreation
Before launching STA tool, all constraints must be defined.
The user must define:
createClock for clock coming from a port. Refer to #Sta_constraints_Clock_creation.
createGeneratedClock if a clock is generated inside the fabric. Refer to #Sta_constraints_Generated_clock_creation.
addFalsePath in order to remove paths to ignore. Refer to #Sta_constraints_Path_between_registers.
TimingDriven
TimingDriven option can be set with the following constraint:
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