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• NG-ULTRA is now available on NX design suite tools

• Timing Driven

Static Timing Analysis (STA)

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• Nanoxplore Design Contraints (NxDC) : The following python methods are compliant with NxMap:

  • reportTiming (from register to register)

  • CreateClock

  • CreateGeneratedClock

  • SetClockGroup

  • SetFalsePath

  • SetMulticyclePath

  • SetMin/MaxDelay

  • SetInput/OutputDelay

  • SetCaseAnalysis

  • SetAnalysisConditions

  • DevelopCKGs

GUI

• New interface

  • Docks can be move independently on main windows or move apart

  • Docks:

    • Interpreter allow to write python method

    • Dashboard show shows a reduction of global floorplan view

    • Selection allow:

      • Selection tab on all element with filter bound to “Command” selection.

      • Detailed information on selected elements

        • Select paths: Provide STA information on the selected path

        • Select instance:

          • Hierarchy level, Region and Module information

          • Source file and TILE/CGB location

          • Input/output net name

          • Configuration information

      • Dynamic SetSite management

    • Regions :

      • Show all Regions and Modules Module and region with utilization details

      • Create/Resize/Delete Region dynamically

      • Assign Module to a new Region dynamically

      • Clipboard and generate python file with all Region/Module/SetSIte/(DSP/RAM)Location

  • Command:

    • Select paths :

      • Longest/Shortest path selection

      • New clock domain selection

      • Detail STA report on selected path

  • Floorplanning overview (Prepared):

    • Refresh fabric element dispatch after Region/Module modification in order to visualized new floorplanning

• Information given in nxmap can be copy/past from GUI

• Select Instance has been improve:

  • More details on each fabric element are available

  • Dynamic SetSite is available at Preplaced step.

  • Filter selection improve

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Constraints

• Constrainpath with DSP : Source and destination registers inside a same DSP can be attached independently by different constrainpath.

• Method exportSites: to export placement constraints for LUTs, DFFs, RAMs, RFs, DSPs, CYs of the design

• Method rejectLowskew: to avoid routing signals into lowskew tree. Can replace NX_BD instanciation.

• Method addBlackBox: to add preplaced IP into design

• NxRegExp update:

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• NXCore IPs can be update independently of nxmap.

• New interface

• NXScopeV2: New NXScope IP is compliant and can be used in NG-ULTRA

Bug

Constraint

• addMappingDirective for a RAM in DFF : Tool was not able to map a RAM into DFF if infered memory is compiled in a library

• NXScopeV2:

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