Feature
NG-ULTRA is now available on NX design suite tools
Timing Driven
Static Timing Analysis (STA)
Nanoxplore Design Contraints (NxDC) : The following python methods are compliant with NxMap:
reportTiming (from register to register)
CreateClock
CreateGeneratedClock
SetClockGroup
SetFalsePath
SetMulticyclePath
SetMin/MaxDelay
SetInput/OutputDelay
SetCaseAnalysis
SetAnalysisConditions
DevelopCKGs
GUI
New interface
Docks can be move independently on main windows or move apart
Docks:
Interpreter allow to write python method
Dashboard shows a reduction of global floorplan view
Selection:
Selection tab on all element with filter bound to “Command” selection.
Detailed information on selected elements
Select paths: Provide STA information on the selected path
Select instance:
Hierarchy level, Region and Module information
Source file and TILE/CGB location
Input/output net name
Configuration information
Dynamic SetSite management
Regions :
Show all Regions and Modules with utilization details
Create/Resize/Delete Region dynamically
Assign Module to a new Region dynamically
Clipboard and generate python file with all Region/Module/SetSIte/(DSP/RAM)Location
Command:
Select paths :
Longest/Shortest path selection
New clock domain selection
Detail STA report on selected path
Floorplanning overview (Prepared):
Refresh fabric element dispatch after Region/Module modification in order to visualized new floorplanning
Information given in nxmap can be copy/past from GUI
Constraints
Constrainpath with DSP : Source and destination registers inside a same DSP can be attached independently by different constrainpath.
Method exportSites: to export placement constraints for LUTs, DFFs, RAMs, RFs, DSPs, CYs of the design
Method rejectLowskew: to avoid routing signals into lowskew tree. Can replace NX_BD instanciation.
Method addBlackBox: to add preplaced IP into design
NxRegExp update:
p.addFalsePath('getPort(cpt_in[0])','getRegisters(“cpt_in_p_reg\[[0-3]\]”)') => p.addFalsePath(getPort(“cpt_in[0]”),getRegisters(“cpt_in_p_reg['[0-3]']”))
Primitive
Header: Get NxMap release information in nxLibrary files headers
SERDES primitives : implement “locked” in generics
Logging
Module instance reporting: Indicates memories and operators used in each design module
Infinite loop reporting: Logs give the net + the file and line
Register optimization: Get information about optimized registers in registers.rpt
Module and Region in STA: Get the associated region and module in STA detailed path
DFF reporting : Get type of the DFF (DFF/DFR) in registersSummary.rpt + get number of DFF by primitive (FE/DSP/RAM/PAD)
Operator in LUT: Adders mapped in LUT appear in reports
Netlist
Header: Get NxMap release information in a header
Tool
Saved STA: STA can be saved in .nym projects setting 'SaveTiming' option to 'Yes'
Large multiplication in ULTRA: compliance with much larger multiplication using CY for adders for better STA optimization
Compilation in NX library: NX is a forbidden library to compile
NXCore
NXCore IPs can be update independently of nxmap.
New interface
NXScopeV2: New NXScope IP is compliant and can be used in NG-ULTRA
Bug
Constraint
addMappingDirective for a RAM in DFF : Tool was not able to map a RAM into DFF if infered memory is compiled in a library
NXScopeV2:
Primitive
Logging
NX_DFF reporting : NX_DFF primitive in the design is now reported
addFalsePath all registers, if source or target is empty, number of found registers is *
Netlist
NX_HSSL_L: netlist generation is now compliant with NX_HSSL_L primitive
NX_PLL_L: use_pll generic is now mapped
Tool
Attributes: attributes were ignored in some cases + log during synthesis added
Differential pad with suffix : pads with suffixes like “_DQS_SWDI” were not able to be configured in differential mode
DSP registers with asynchronous reset : asynchronous reset DFF cannont be merged in DSP