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  • Nanoxplore Design Contraints (NxDC) : The following python methods are compliant with NxMap:

    • reportTiming (from register to register)

    • CreateClock

    • CreateGeneratedClock

    • SetClockGroup

    • SetFalsePath

    • SetMulticyclePath

    • SetMin/MaxDelay

    • SetInput/OutputDelay

    • SetCaseAnalysis

    • SetAnalysisConditions

    • DevelopCKGs

  • Previous Python STA methods are kept compatible on this version but will be deprecated in next version. All STA constraints are translate into the new format inside log.

  • STA can be saved in .nym projects setting 'SaveTiming' option to 'Yes'

GUI

  • New interface

    • Docks can be move independently on main windows or move apart

    • Docks:

      • Interpreter allow to write python method

      • Dashboard shows show a reduction of global floorplan view

      • Selection:

        • Selection tab on all element elements with filter bound to “Command” selection.

        • Detailed information informations on selected elements

          • Select paths: Provide STA information informations on the selected path

          • Select instance:

            • Hierarchy level, Region and Module informationinformations

            • Source file and TILE/CGB location

            • Input/output net name

            • Configuration informationinformations

        • Dynamic SetSite management

      • Regions :

        • Show all Regions and Modules with utilization details

        • Create/Resize/Delete Region dynamically

        • Assign Module to a new Region dynamically

        • Clipboard and generate python file with all Region/Module/SetSIte/(DSP/RAM)Location

    • Command:

      • Select paths :

        • Longest/Shortest path selection

        • New clock domain selection

        • Detail STA report on selected path

    • Floorplanning overview (Prepared):

      • Refresh fabric element dispatch after Region/Module modification in order to visualized new floorplanning

  • Information given in nxmap can be copy/past from GUI

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Python method

  • Constrainpath with DSP : Source and destination registers inside a same DSP can be attached independently by different constrainpath.

  • Method exportSites: to export placement constraints for LUTs, DFFs, RAMs, RFs, DSPs, CYs of the design

  • Method rejectLowskew: to avoid routing signals into lowskew tree. Can replace NX_BD instanciation.

  • Method addBlackBox: to add preplaced IP into design

  • NxRegExp update:

...

  • Header: Get NxMap release information in nxLibrary files headers

  • SERDES primitives : implement “locked” in generics

Logging

  • Module instance reporting

Report

  • Reports have new format and more informations

  • Hierarchy.rpt: Indicates memories and operators used information in each design modulehierarchy level

  • Infinite loop reporting: Logs give the net + the file and line

  • Register optimizationRegisters.rpt: Get information about optimized registers in registers.rpt

  • Module and Region in STA report: Get the associated region information on Region and module associate to each element in STA detailed path

  • DFF reporting registersSummary.rpt : Get type of the DFF (DFF/DFR) in registersSummary.rpt + get number of DFF by primitive (FE/DSP/RAM/PAD)

  • Operator in LUT.rpt:

    • Adders mapped in LUT appear in reports

    • Automatic LUT and logic level evaluation is given for all operator

  • addFalsePath : all registers, if source or target is empty, number of found registers is *

  • Design Constraints : report all STA constraints

  • NX_DFF primitive in the design is now reported

Netlist

  • Header: Get NxMap release information in a header

Tool

  • Saved STA: STA can be saved in .nym projects setting 'SaveTiming' option to 'Yes'NX_HSSL_L: netlist generation is now compliant with NX_HSSL_L primitive

  • NX_PLL_L: use_pll generic is now mapped

Tool

  • Large multiplication in ULTRA: compliance with much larger multiplication using CY for adders for better STA optimization

  • Compilation in NX library: NX is a forbidden library to compile

NXCore

  • NXCore IPs can be update independently of nxmap.

  • New interface

  • NXScopeV2: New NXScope IP is compliant and can be used in NG-ULTRA

Bug

Constraint

  • addMappingDirective for a RAM in DFF : Tool was not able to map a RAM into DFF if infered memory is compiled in a library

  • NXScopeV2:

Primitive

Logging

  • NX_DFF reporting : NX_DFF primitive in the design is now reported

  • addFalsePath all registers, if source or target is empty, number of found registers is *

Netlist

  • NX_HSSL_L: netlist generation is now compliant with NX_HSSL_L primitive

  • NX_PLL_L: use_pll generic is now mapped

...

  • Attributes: attributes were ignored in some cases + log during synthesis added

  • Differential pad with suffix : pads with suffixes like “_DQS_SWDI” were not able to be configured in differential mode

  • DSP registers with asynchronous reset : asynchronous reset DFF cannont can’t be merged in DSP

NXCore

  • NXCore IPs can be update independently of nxmap.

  • New interface

  • NXScopeV2: New NXScope IP is compliant with all FPGA

Bug

  • NXScopeV2: Generation issue. Update will be provide on our website.

  • NXScopeV1: NXScope is not compliant with NG-ULTRA

  • SDF : NX_RAM in ECC Fast does not get tipd for ACKD/BCKD

  • Vcore voltage given in SDF files and STA files in NG-ULTRA are NG-MEDIUM/LARGE core value.