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Group | Pin name | I, O or I/O | User I/O | During configuration | |||||
Required | Impacted | Pin behavior | |||||||
GLOBAL | MODE(2:0) | I | No | Yes | 000 | Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’ | |||
ID(3:0) | I | No | Yes | - | Device Identification. It must comply with the bitstream device id to allow access bitstream loading or the bitstream device id e equal to 0xF (broadcast mode). | ||||
FABRIC_USER(3:0) | I | Yes | No | - | Additional IO for user. FABRIC_USER[0] can be connected to low-skew network. | ||||
CLK | I | No | Yes | - | Always required. Must be routed to an external clock in the range [0MHz;100MHz]. | ||||
RST_HARD_N | I | No | Yes | - | Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds. | ||||
RST_SOFT_N | I | No | No | - | It only resets internal configuration registers but does not apply a reset on the configuration memory. | ||||
READY | O | No | No | Yes | Goes high when the configuration is complete (the FPGA enters in user’s mode) | ||||
TRIGGER | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | ||||
ERROR | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. | ||||
POK | O | No | No | No | Goes high when VDD1V2 Core and VDD2V5A Analog Supply are on. | ||||
Slave Parallel 8 | CS | I | No | No | Yes | Unused but unavailable. Must be left unconnected | |||
TYPE[1:0] | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
DATA_OE | O | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
D(7:0) | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
Slave par ext | D(8) | O | No | Yes | - | External memory Chip Select (active Low) Requires a diode + Pull-Up (see diagram) When the bitstream download is completed this pin is driven to ‘1’ | |||
D(9) | O | No | Yes | - | External bitstream memory Clock When the bitstream download is completed this pin is driven to ‘0’ | ||||
D(10) | I | No | Yes | - | MISO (data in from external memory) | ||||
D(11) | O | No | Yes | - | MOSI (data out to external memory) When the bitstream download is completed this pin is driven to ‘0’ | ||||
D(12) | I | Yes | No | No | Available as User’s I/O | ||||
D(13) | I/O | Yes | No | No | Available as User’s I/O | ||||
D(14) | I/O | Yes | No | No | Available as User’s I/O | ||||
D(15) | I/O | Yes | No | No | Available as User’s I/O | ||||
SPACEWIRE | DIN_P | I | Yes(*) | No | No | When Master Serial SPI is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application. | |||
DIN_N | I | Yes(*) | No | No | |||||
SIN_P | I | Yes(*) | No | No | |||||
SIN_N | I | Yes(*) | No | No | |||||
DOUT_P | O | Yes(*) | No | No | |||||
DOUT_N | O | Yes(*) | No | No | |||||
SOUT_P | O | Yes(*) | No | No | |||||
SOUT_N | O | Yes(*) | No | No | |||||
JTAG | TCK | I | No | No | No | JTAG is available in all modes. Don’t use it while configuration is in progress. | |||
TMS | I | No | No | No | |||||
TDI | I | No | No | No | |||||
TRST_HARD_N | I | No | No | No | |||||
TDO | O | No | No | No | |||||
...
Group | Pin name | I, O or I/O | User I/O | During configuration | |||||
Required | Impacted | Pin behavior | |||||||
GLOBAL | MODE(2:0) | I | No | Yes | 001 | Input pins sampled at power-up. MODE(2:0). They define the configuration mode to be used for NG-LARGE configuration. MODE(2:0) cannot be changed when RST_HARD_N = ‘1’ | |||
ID(3:0) | I | No | Yes | - | Device Identification. It must comply with the bitstream device id to allow access bitstream loading. | ||||
FABRIC_USER(3:0) | I | Yes | No | - | Additional IO for user. FABRIC_USER[0] can be connected to low-skew network. | ||||
CLK | I | No | Yes | - | Always required. Must be routed to an external clock in the range [0MHz;100MHz]. | ||||
RST_HARD_N | I | No | Yes | - | Mandatory input. When low, it resets the internal configuration engine. RST_HARD_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_HARD_N goes high, the configuration starts after up to 3 additional microseconds. | ||||
RST_SOFT_N | I | No | No | - | It only resets internal configuration registers but does not apply a reset on the configuration memory. | ||||
READY | O | No | No | Yes | Goes high when the configuration is complete (the FPGA enters in user’s mode) | ||||
TRIGGER | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated TRIGGER_MASK. | ||||
ERROR | O | No | No | Yes | Generates a high-level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration and during design processing. Error is taken into account only if it is not masked by the associated ERROR_MASK. | ||||
POK | O | No | No | No | Goes high when VDD1V2 Core and VDD2V5A Analog Supply are on. | ||||
Slave Parallel | CS | I | No | No | Yes | Unused but unavailable. Must be left unconnected | |||
TYPE[1:0] | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
DATA_OE | O | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
D(7:0) | I | No | No | Yes | Unused but unavailable. Must be left unconnected | ||||
Slave Par ext | D(8) | O | No | Yes | - | External memory Chip Select (active Low) Requires a diode + Pull-Up (see diagram) When the bitstream download is completed, this pin is driven to ‘1’ | |||
D(9) | O | No | Yes | - | External bitstream memory Clock When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(10) | I | No | Yes | - | MISO (data in from external memory) | ||||
D(11) | O | No | Yes | -- | MOSI (data out to external memory) When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(12) | I | Yes | No | No | Available as User’s I/O | ||||
D(13) | I/O | Yes | Yes | - | To Vcc SPI Flash memory When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(14) | I/O | Yes | Yes | - | To Vcc SPI Flash memory When the bitstream download is completed, this pin is driven to ‘0’ | ||||
D(15) | I/O | Yes | Yes | - | To Vcc SPI Flash memory When the bitstream download is completed, this pin is driven to ‘0’ | ||||
SPACEWIRE | DIN_P | I | Yes(*) | No | No | When Master Serial SPI with Vcc Control is selected the SpaceWire internal IP can be used after completing the configuration (*) The SpaceWire internal IP is available for the user’s application. | |||
DIN_N | I | Yes(*) | No | No | |||||
SIN_P | I | Yes(*) | No | No | |||||
SIN_N | I | Yes(*) | No | No | |||||
DOUT_P | O | Yes(*) | No | No | |||||
DOUT_N | O | Yes(*) | No | No | |||||
SOUT_P | O | Yes(*) | No | No | |||||
SOUT_N | O | Yes(*) | No | No | |||||
JTAG | TCK | I | No | No | No | JTAG is available in all modes. Don’t use it while configuration is in progress. | |||
TMS | I | No | No | No | |||||
TDI | I | No | No | No | |||||
TRST_HARD_N | I | No | No | No | |||||
TDO | O | No | No | No | |||||
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