Table of Content
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Ports | Direction | Type | Description |
REF | In | std_logic | Reference clock input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled. |
FBK | In | std_logic | External FeedBack input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) |
VCO | Out | std_logic | VCO output : Fvco = fbk_intdiv * 2**(fbk_div_on - ref_div_on + 1) * clk_ref_freq Connectivity: WFG inputs |
D1…D3 | Out | std_logic | Divided clocks. Fvco frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128 Important note: D1, D2 and D3 outputs are reset while PLL RDY is not asserted. Connectivity: WFG inputs |
OSC | Out | std_logic | Internal 200 MHz oscilator Connectivity :WFG inputs, delay calibration system |
RDY | Out | std_logic | High when PLL is locked Connectivity: RDY inputs of WFGs, fabric… |
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VCO: the output of the VCO
DIVP1, DIVP2 and DIVP3 : three outputs generated by frequency division (power of 2) of the VCO output
DIVO1 and DIVO2 : two additional outputs generated by frequency division (odd ratio) of the VCO output
LDFO : This is the output of the internal feedback divider (divides by (fbk_intdiv + 2) * 2 ). Note that LDFO output can be also directed to WFG for clock generation, and the used as external feedback.
OSC: Internal 200 MHz output coming from 400MHz internal oscillator output (used for delays calibration on the PLL feedback path, WFG internal delays and input/output delays). OSC output can also be used as auxiliary clock.
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The delays calibration system uses the PLL 200 MHz output coming from oscillator output as reference clock to calibrate all delays: feedback path in the PLL itself, WFG delays in same CKG), and IO delays in the two neighboring complex and simple IO banks:
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Ports | Direction | Type | Description |
REF | In | std_logic | Reference clock input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled. |
FBK | In | std_logic | External FeedBack input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) |
R | In | std_logic | Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL |
VCO | Out | std_logic | VCO output: - Internal feedback: Fvco = 2 * (fbk_intdiv + 2) * clk_ref_freq / (ref_intdiv + 1) - External feedback: Fvco = (pattern_end + 1) / n_sim_pat * clk_ref_freq / (ref_intdiv + 1) Where n_sim_pat is the number of similar patterns sequence found in pattern_end+1 MSB bits of pattern. |
REFO | Out | std_logic | Output of the REFerence divider. The division factor is set by the generic “ref_intdiv” |
LDFO | Out | std_logic | Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv” |
DIVP1 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp1” |
DIVP2 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp2” |
DIVP3 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp3o2” |
DIVO1 | Out | std_logic | This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divouto1” |
DIVO2 | Out | std_logic | This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divoutp3o2” |
OSC | Out | std_logic | Internal 200 MHz coming from 400MHz internal oscilator Connectivity :WFG inputs, delay calibration engine |
PLL_LOCKED | Out | std_logic | High when PLL is locked Connectivity: RDY inputs of WFGs, fabric… |
CAL_LOCKED | Out | std_logic | High when the automatic calibration procedure of the current FPGA quarte area is complete Connectivity: fabric |
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