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By default, adders are mapped into Carry and Multipliers in DSP. But it can sometimes be interesting to change default mapping directives.

Check #Mapping_Directive_Operator for information about constraint setting.

Memory

Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction thanks to addMappingDirective method described in Nxmap user manual.

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In case of memory with reset assertion, the memory has to be mapped into DFF as RF or RAM does not have a reset input pin.

Check #Mapping_Directive_Memory for information about constraint setting.

Placing

In order to improve the maximum clock frequency for each clock domain, it is advised to follow the following steps:

• Define a floor plan for the design depending on module relationships and pinout.

• Apply the floor plan to your NXmap project using confineModule described in Nxmap user manual. Check #Floor_planning_Constrain_module for information about constraint setting.

• If needed, repeat this process going deeper and deeper in the design hierarchy.

• For last most critical paths, use constrainPath described in Nxmap user manualin order to create a region with only a few elements contained into the specified path. Check #Floor_planning_Constrain_path_between_registers for information about constraint setting.

It can also have a very positive impact to create unitary projects and reuse the routed projects as a blackbox in your final top project using addBlackBox described in Nxmap user manual.

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• addPLLLocation for PLL instance in a CKG. addWFGLocation for Check #Instance_placing_Ring_placing for information about constraint setting.

• addWFGLocation for WFG instance in a CKG and a WFG spot. Check #Instance_placing_Ring_placing for information about constraint setting.

• addRAMLocation for RAM instance in a CGB. Check #Instance_placing_Ram_placing for information about constraint setting.

• addDSPLocation for DSP instance in a CGB and a DSP spot. Check #Instance_placing_Dsp_placing for information about constraint setting.

• setSite for LUT/DFF/CY in a TILE.

How to use NXpython constrains methods

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• Check #Instance_placing_Tile_placing for information about constraint setting.

How to use NXpython constrains methods

Mapping directive

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Mapping_directive_Operator Mapping_directive_Operator

Operator

In order to map an operator into LUT, CY or DSP, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the operator model or instance in operators.rpt report. For instance, “ | Operator 'add_3u_3u' | : add_L25 (line 25 in …”, model name is “add_3u_3u” and instance name is “add_L25”.

• Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(add_3u_3u)','ADD','DSP')” or p.addMappingDirective('getInstances(add_L25)','ADD','DSP')”, and relaunch the project.

• Check in operators.rpt report the constraint matched with the desired instance.

Please have a look at Training Package Application Note MappingDirective/Operator project.

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Mapping_directive_Memory Mapping_directive_Memory

Memory

In order to map an operator into FE, RF, RAM or RAM_ECC, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the memory model in memories.rpt report. For instance, “ | Ram 'RAM_s_mem' Analysis:”, model name is “RAM_s_mem”.

• Add the constraint specifying instance to map the operator, for instance “ p.addMappingDirective('getModels(RAM_s_mem)','RAM','RAM_ECC')”, and relaunch the project.

• Check in memories.rpt report the constraint matched with the desired instance.

Instance placing

Please have a look at Training Package Application Note MappingDirective/Memory project.

Instance placing

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Instance_placing_Dsp_placing Instance_placing_Dsp_placing

DSP placing

In order to place manually an inferred DSP in a CGB spot, follow the following steps:

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Please have a look at Training Package Application Note PlacingConstraint/DspLocation project.

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RAM placing

In order to place

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Instance_placing_Ram_placing Instance_placing_Ram_placing

RAM placing

In order to place manually an inferred RAM in a CGB spot, follow the following steps:

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Please have a look at Training Package Application Note PlacingConstraint/RamLocation project.

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Instance_placing_Ring_placing Instance_placing_Ring_placing

Ring placing

In order to place manually an automatically created WFG in a CKG spot, follow the following steps:

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Please have a look at Training Package Application Note PlacingConstraint/RingLocation project.

Tile placing

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Instance_placing_Tile_placing Instance_placing_Tile_placing

Tile placing

In order to place manually an inferred TILE instance like DFF, LUT or CY, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the register name in RegisterSummary.rpt report or in timing files. For instance, i_cpt_0|s_cpt_out_reg[5]”.

• Add the constraint specifying TILE spot (TILE coordinates), for instance “p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]'”, and relaunch the project.

• Check in preplaced.rpt report the constraint matched with the desired instance.

Please have a look at Training Package Application Note PlacingConstraint/Site project.

Floor planning

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Floor_planning_Complexity Floor_planning_Complexity

Complexity

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In order to confine a module (component get complexity for each module of the design hierarchy) in a region containing TILE, CGB and MESH, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the module and instance name in hierarchy.rpt report. For instance, “| ~ |-> row_coltiming_pipe(X212B9C19X2A98C8C6) [ GEN_HIER0|GEN_ROW[0].ROW_PIPE ]”, module name is “ |-> row_coltiming_pipe(X212B9C19) X2A98C8C6)” and instance name is “[ GEN_HIER0|GEN_ROW[0].ROW_PIPE ]”.

• Add the constraint specifying area coordinates, for instance “p.constrainModuleaddModule('|-> row_coltiming_pipe(X212B9C19X2A98C8C6) [ GEN_HIER0 ]', 'GEN_HIER0.GEN_ROW_M','Soft',9,6,2,3[0].ROW_PIPE', 'GEN_HIER0_ROW_R-%',False)”, and relaunch the project.

• Check in hierarchy.rpt report the constraint matched with the desired instance.

Please have a look at Training Package Application Note PlacingConstraint/Region project.

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Floor_planning_Constrain_module Floor_planning_Constrain_module

Constrain Module

In order to confine all instances in a path between 2 registers a module (component of the design hierarchy) in a region containing TILE, CGB and MESH, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timingmodule name in hierarchy.rpt report. For instance, “module0“| submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1~ |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”, name is “|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]”.

• Add the constraint specifying area coordinates, for instance “p.constrainPathconstrainModule('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','PIPEGEN_HIER0_REGROW_M','Soft',9,6,2,3,'PIPEGEN_HIER0_REGROW_R',False)”, and relaunch the project.

• Check in hierarchy.rpt report the constraint matched with the desired instance.

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Please have a look at Training Package Application Note PlacingConstraint/Region project.

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Floor_planning_Constrain_path_between_register Floor_planning_Constrain_path_between_register

Constrain path between registers

In order to confine all instances in a path between 2 registers in a region containing TILE, CGB and MESH, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.

• Add the constraint specifying area coordinates, for instance “p.constrainPath('|-> row_col_pipe(X212B9C19) [ GEN_HIER0 ]','PIPE_REG_M','Soft',9,6,2,3,'PIPE_REG_R',False)”, and relaunch the project.

• Check in hierarchy.rpt report the constraint matched with the desired instance.

Please have a look at Training Package Application Note PlacingConstraint/ConstrainPath project.

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Floor_planning_Preplace_ip Floor_planning_Preplace_ip

Preplace IP

In order to preplace a macro IP of a global design in order to reach design specifications (delays, maximum frequencies, …) in an area of the chip before integrating it in the global design, follow the following steps:

• Define the macro IP as the top cell.

• Define a minimum aperture and all needed constraints as it was a global project to reach specifications. Save the project file after routed steps.

• Do not declare the macro IP entity file in the global project. Instead, add the macro IP as a blackbox, specifying coordinates of the top left corner of the macro IP aperture in the global project, for instance “p.addBlackBox('switch_counter',IP','../switch_counter_preplaced.nym','g_inst.i_switch_counter_0:1x8')”.

• Check in synthesize.log llog the constraint matched.

Please have a look at Training Package Application Note PlacingConstraint/Preplace project.

STA constraints

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Sta_constraints_Clock_declaration Sta_constraints_Clock_declaration

Clock declaration

In order to declare a clock in your project in order to get required frequencies in logs, follow the following steps:

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Please have a look at Training Package Application Note StaConstraint/GeneratedClock project.

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Sta_constraints_Constrain_path_between_registers Sta_constraints_Constrain_path_between_registers

Constrain path between registers

In order to declare a path between 2 registers as a false path, multi-cycle path, min or max delay path, follow the following steps:

• Launch your design for the first time without constraint.

• Grab the source and target register in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing. For instance, “module0|submodule0|pipe_reg[0].CK” and “module0|submodule0|pipe_reg[1].CK” , names are “module0|submodule0|pipe_reg[0]” and “module0|submodule0|pipe_reg[1]”.

• Add the constraint specifying area coordinates, for instance “p.addFalsePath('getRegisters(module0|submodule0|pipe_reg[0])','getRegisters(module0|submodule0|pipe_reg[0])')”, and relaunch the project.

• Check in DOMAIN_<clk1>_to_<clk2>_<progress_step>_<conditions>.timing.rpt timingt report the path no longer appears.

Please have a look at Training Package Application Note StaConstraint/FalsePath project.