Table of Content
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Ports | Direction | Type | Description |
REF | In | std_logic | Reference clock input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled. |
FBK | In | std_logic | External FeedBack input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) |
VCO | Out | std_logic | VCO output : Fvco = fbk_intdiv * 2**(fbk_div_on - ref_div_on + 1) * clk_ref_freq Connectivity: WFG inputs |
D1…D3 | Out | std_logic | Divided clocks. Fvco frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128 Important note: D1, D2 and D3 outputs are reset while PLL RDY is not asserted. Connectivity: WFG inputs |
OSC | Out | std_logic | Internal 200 MHz oscilator Connectivity :WFG inputs, delay calibration system |
RDY | Out | std_logic | High when PLL is locked Connectivity: RDY inputs of WFGs, fabric… |
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Example : location => “CKG2.PLL1”
cfg_use_pll
type bit
default value '1'
Set to 1 to enable the PLL. When set to 0, the PLL is bypassed with Fvco = Frefo.
ref_intdiv
type integer (range 0 to 31)
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Ports | Direction | Type | Description |
REF | In | std_logic | Reference clock input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled. |
FBK | In | std_logic | External FeedBack input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) |
R | In | std_logic | Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL |
VCO | Out | std_logic | VCO output: - Internal feedback: Fvco = 2 * (fbk_intdiv + 2) * clk_ref_freq / (ref_intdiv + 1) - External feedback: Fvco = (pattern_end + 1) / n_sim_pat * clk_ref_freq / (ref_intdiv + 1) Where n_sim_pat is the number of similar patterns sequence found in pattern_end+1 MSB bits of pattern. |
REFO | Out | std_logic | Output of the REFerence divider. The division factor is set by the generic “ref_intdiv” |
LDFO | Out | std_logic | Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv” |
DIVP1 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp1” |
DIVP2 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp2” |
DIVP3 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp3o2” |
DIVO1 | Out | std_logic | This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divouto1” |
DIVO2 | Out | std_logic | This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divoutp3o2” |
OSC | Out | std_logic | Internal 200 MHz oscilator Connectivity :WFG inputs, delay calibration engine |
PLL_LOCKED | Out | std_logic | High when PLL is locked Connectivity: RDY inputs of WFGs, fabric… |
CAL_LOCKED | Out | std_logic | High when the automatic calibration procedure of the current FPGA quarte area is complete Connectivity: fabric |
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| Code Block | ||
|---|---|---|
| ||
-- In this example :
-- Fref = 25 MHz (and “ref_intdiv” = 0 for division factor of 1
-- Fldfo = 25 MHz (used as feedback)
-- Fvco = 400 MHz (25 MHz x (“fbk_intdiv” + 2) * 2 = 25 MHz * 16
-- Please note that Fvco must be in the range 200 to 800 MHz
-- Fdivp1 = 400 MHz / (2 ** “clk_outdivp1”) = 400 MHz / 8 = 50 MHz
-- Fdivp2 = 400 MHz / (2 ** (“clk_outdivp2” + 1)) = 400 MHz / 32 = 12.5 MHz
-- Fdivp3o2 = 400 MHz / (2 ** (“clk_outdivp3o2” + 2)) = 400 MHz / 64 = 6.25 MHz
-- Fdivo2 = 400 MHz / ((2 * “clk_outdivp3o2”) + 5) = 400 MHz / 13 = 30.77 MHz
-- Fdivo1 = 400 MHz / ((2 * “clk_outdivo1”) + 3)) = 400 MHz / 9 = 44.44 MHz
PLLUT : NX_PLL_L
generic map (
location => “CKG2.PLL1”,
cfg_use_pll => '1',
ref_intdiv => 0, -- 0 to 31 ((N+1 : (%1 to %32) -- 0 for div by 1
ref_osc_on => '0', -- 0: disabled - 1: enabled
ext_fbk_on => '0', -- 0: disabled - 1: enabled
fbk_intdiv => 6, -- 0 to 31 ((N+2)*2 : %4 to %66 by step 2) -- Div by 16
fbk_delay_on => '0', -- 0: no delay - 1: delay
fbk_delay => 0, -- 0 to 63
clk_outdivp1 => 3, -- 0 to 7 P1 (2^n : %1 to %128) -- Div by 8
clk_outdivp2 => 4, -- 0 to 7 P2 (2^(n+1): %2 to %256) -- Div by 32
clk_outdivo1 => 3, -- 0 to 7 O1 ((2n)+3 : %3 to %17) -- Div by 7
clk_outdivp3o2 => 4 -- 0 to 7 P3 (2^(n+2): %4 to %512) -- P3 : Div by 64
-- O2 ((2n)+5 : %5 to %19) -- O2 : Div by 13
)
port map (
REF => REFIN,
FBK => FBK,
R => RST,
VCO => VCO, -- VCO = 400 MHz
LDFO => LDFO, -- LDFO = 50 MHz
REFO => REFO,
DIVO1 => DIVO1, -- DIVO1 = 57.14 MHz
DIVO2 => DIVO2, -- DIVO2 = 30.77 MHz
DIVP1 => DIVP1, -- DIVP1 = 50 Mhz
DIVP2 => DIVP2, -- DIVP2 = 12.5 MHz
DIVP3 => DIVP3, -- DIVP3 = 6.25 MHz
OSC => OSC,
PLL_LOCKED => PLL_LOCKED,
CAL_LOCKED => CAL_LOCKED
); |
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type std_logic
default value ‘U’
This generic represents the initial value of the associated DFF. The initial value is set by bitstream. The available values are: ‘U’ for undefined (no value set in bitstream), ‘0’ for low and ‘1’ for high.
dff_edge
type bit
default value ‘0’
This generic represents the front polarity of the clock of the associated DFF. ‘0’ is for rising edge and ‘1’ for falling edge.
dff_init
type bit
default value ‘0’
This generic represents whether the DFF considers the R (reset) input. ‘0’ is for ignore and ‘1’ for using connected net.
dff_load
type bit
default value ‘0’
This generic represents whether the DFF considers the L (load) input. ‘0’ is for ignore and ‘1’ for using connected net.
dff_sync
type bit
default value ‘0’
This generic represents whether the DFF reset is synchronous or asynchronous. ‘0’ is for asynchronous and ‘1’ for synchronous.
dff_type
type integer
default value 0
This generic represents whether the reset must initialize the DFF to 0 or 1. dff_type is set to ‘0’ for reset initializing the DFF to 0, dff_type is set to ‘1’ for reset initializing the DFF to 1. dff_type can also be set to 2 to configure set/reset on signal.
| Note |
|---|
Only dff_type = 0 is allowed for NG-MEDIUM and NG-LARGE. |
Ports
Ports | Direction | Type | Description |
I | input | std_logic | Input |
CK | input | std_logic | Clock |
L | input | std_logic | Load |
R | input | std_logic | Reset |
O | output | std_logic | Output |
...