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This document is intended to guide users on NxMap NXmap software best practice.
The aim is to ease NxMap NXmap using and get the best recommendations in order to implement a project into NanoXplore components.
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All recommendations are divided in several categories depending on product development phase.
They are based mainly on NxPython NXpython methods but some of them can be applied in the GUI.
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Clock management
NanoXplore FPGA FPGAs contain a low-skew network in order to spread signal with high fanout like clock, reset, load signals.
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In order to infer a memory instead of instantiating a NanoXplore primitive (advantage is the user can choose with the same RTL code to map this memory in RF, RAM, RAM_ECC, … thanks to NxPython NXpython constraints), it is recommended to follow TrainingPackage Design/MemInfer examples providing inference for ROM, SRAM, DPRAM with and without ECC.
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It will be very helpful to constrain the design by module then.
Project creation
NxMap NXmap is based on Python scripts that is to say a project is a class and all options and constraints are methods associated to this class.
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In case of starting from scratch, it can be easier to create a project using the GUI in order to get the right basic NxPython NXpython methods.
The project needs the following database:
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| Note |
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Never add a nxLibrary file to your project. NxMap NXmap tool already get the needed files with NX primitives. |
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Set options before any progress.
Set IO pads locations and parameters before any progress.
Save your project after each progress step.
Separate your project in categories (setup,synthesis, placing, routing, sta) and set your constraints at the right place.
Project check
One Once the project is launched, it is necessary to check logs and reports in order to be sure there is not any issue leading to errors, undesired optimizations, …
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If not, a message appears in the console. Sometimes, the message is clear enough, but it couldn’t could not be. So errors.rpt and warning.rpt reports can be very useful in order to grab the issue.
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These errors can be solved by changing the following parameters/options :
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The input clock frequencies and other parameters must be informed to NxMap NXmap for STA.
Please refer to createClock and createGeneratedClock described in Nxmap user manual.
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By default, small memories (equal or less than 64x16) will be mapped into RF and bigger mapped into RAM. But it can sometimes be interesting to change default mapping directives.
It it highly recommended to size the design according to available depths and heights. Otherwise, too many memories will be instantiated and will affect the routing and STA performances.
In case of memory with reset assertion, the memory has to be mapped into DFF as RF or RAM does not have a reset input pin.
Placing
In order to improve the maximum clock frequency for each clock domain, it is advised to follow the following steps:
Define a floor plan for the design depending on module relationships and pinout.
Apply the floor plan to your NxMap NXmap project using confineModule described in Nxmap user manual.
If needed, repeat this process going deeper and deeper in the design hierarchy.
For last most critical paths, use constrainPath described in Nxmap user manualin order to create a region with only a few elements contained into the specified path.
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It is also possible to place manually instances in a specified spot thanks to the following NxPython NXpython methods all described in Nxmap user manual:
addPLLLocation for PLL instance in a CKG.
addWFGLocation for WFG instance in a CKG and a WFG spot.
addRAMLocation for RAM instance in a CGB.
addDSPLocation for DSP instance in a CGB and a DSP spot.
setSite for LUT/DFF/CY in a TILE.
How to use
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NXpython constrains methods
Mapping directive
Operator
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developCKGs method is active by default, NxMap NXmap compute automatically PLL and WFG required frequencies if input clock is declared.
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