nXmap 3.11 Release Notes

Features

Constraint

• [Constraint] setSite() command: compliance with LUT DFF and CY / Constraint can be set at any moment before Placing 1/5 (included)

• [Constraint] constrainPath: DSP, RF, RAM and CY recognized. Distinction between Hard constrainPath (only instances in path are constrained) and Soft constrainpath (registers connected to all instances in path are constrained too).

• [Constraint] reportRegisters: report the list of all registers at any step of progress

• [Constraint] NxRegExp: Check Appendix “NxRegExp”

• [Constraint]: addBlackbox (IP): Preplacing IP and implement the routed project in the top project. All TILE and CGB instances are supported.

Primitive

• [Primitive] NX_GCK: ‘MUX’ mode with input generated into the fabric

• [Primitive] NX_RAM: Input data mapped into RAM registers Samah c’est bien ça ?

Logging

• [Logging] Options table for bitstreaming in logs

• [Logging] Added GCK to reportInstances table

Tool

• [Tool] DSP_U : Inferred large multiplications allowed

• [Tool] addVlogDefine command: command to override ‘Define’ in verilog file

Bug fix

Constraint

• [Constraint] IO: Wrong IO name mustn’t reserve a pad

Logging

• [Logging] Termination: TerminationReference only allowed for pads with termination

• [Logging] Multiple Emitter: Name of the signal concerned by error is reported to user

• [Logging] Termination: No termination for 3.3V for MEDIUM + LARGE / User IO name is reported in case of wrong termination value

Netlist

• [Netlist] NX_IOB: generics set by addPad are now passed through the macro cell

• [Netlist] NX_PLL_U: ‘use_cal’ set as integer instead of std_logic

Appendix

NxRegExp

Impacted methods:

The following methods allow regular expressions / wildcard formats in order to match with multiple instances:

·       addDSPLocation

·       addModule

·       addRAMLocation

·       constrainPath

·       getInstances

·       getModels

·       getRegisters

·       setSite

·       …

Maintainability:

It is no longer necessary to escape (with the ‘\’ character) special characters for these methods.

Affected special characters are:

·       ‘[‘

·       ‘]’

·       ‘(‘

·       ‘)’

·       ‘|’

For instance, the constraint:

addModule('timing_pipe\(X2A98C8C6\)', 'GEN_HIER0.GEN_COL\[0\].COL_PIPE', 'GEN_HIER0_COL-%')

can be replaced by:

addModule('timing_pipe(X2A98C8C6)', 'GEN_HIER0.GEN_COL[0].COL_PIPE', 'GEN_HIER0_COL-%')

However, the old format is still compliant and still operates.

User use:

In a usual way, a copy/paste of a path from a log file works for the constraint.

In addition, it is comfortable to use ‘*’ and ‘+’ characters to match several paths.

‘*’ matches with any character: can be very useful to match with all paths beginning with a specified path.

‘+’ matches with any character but ‘|’: can be very useful to match with all paths beginning with a specified path without matching with lower hierarchy levels.

Hereafter an example with existing paths and constraints: