Table of Content

Introduction

The CMIC is an embedded engine performing automatic verification and repair of the configuration memory.

CMIC reference memory is integrated into the FPGA and contains all references signatures to verify the configuration memory integrity.

This memory is initialized during the bitstream download process with reference data computed by NXmap software.

By default, the CMIC is disable.

CMIC Operation

CMIC Definition

CMIC is the module that checks the integrity of the configuration memory.

The bitstream manager downloads the bitstream (Design configuration + CMIC reference memory). CMIC memory is included in the FPGA.

The fabric is divided into 5 rows of 28 columns each division is a region.

Each region is made of configuration word lines and is protected with 4 signatures.

The CMIC memory contains all signatures which allows to detect 2 errors and correct 1 error by word line in the configuration memory.

The total correction capacity is 560 simple errors.

Each configuration word line will be checked/corrected by CMIC.

At startup, a CMIC verification is made before the rising edge of “ready” signal on the prog bank.

CMIC storage

The CMIC has its own memory protected by ECC in the FPGA.

The ECC can correct 1 error and detect 2 errors.

The ECC will correct automatically the single error detected in the CMIC memory.

The CMIC does not need to access the external memory (used to store the bitstream) when performing checks and repairs at run time.

The CMIC process needs to be activated during the bitstream generation.

CMIC Reference Generation

CMIC Sequencing

Once the initialization is done, the CMIC engine can be periodically activated to perform the following sequence:

1. Read configuration data

2. Calculate signature

3. Compare the signature with CMIC reference

4. If a mismatch is detected:

a. Calculate faulty bit location

b. Read configuration data

c. Repair flipped bit

d. Write configuration data

At the end of the configuration process if CMIC is enabled an automatic CMIC verification is made before the ready flag rise.

A successful verification notification signals is generated:

READY: NG-MEDIUM output pin. Goes high after successful configuration. When READY goes high, the user’s I/O banks are activated and NG-MEDIUM enters in user’s defined behavior mode.

To check if an uncorrectable error has been found the user has to read the ERROR1 and ERROR2 registers. Please refer to NanoXplore_NX1H35AS_Configuration_Guide documentation.

In case of uncorrectable error, the bitstream must be reloaded by asserting RST_N to low level during at least 50 CLK cycles – or 3 us (to reset the internal configuration engine), before going high to restart the configuration process.

Additional related CMIC signals can be monitored in the FPGA fabric as part of the NG-MEDIUM interface, located in the programming bank. This includes:

• CMIC_CORR(10:0): 11-bit counter value that gives the number of corrected errors on fabric configuration.

• Upon configuration, READY is asserted (high) when the bitstream is loaded and a first CMIC cycle has been successfully executed (if CMIC is not disable).

CMIC Activation/Deactivation

By default, the CMIC is deactivated,

The CMIC can be directly activated in NXmap, this option is documented in NXmap_user_manual.

The CMIC can be activated/deactivated by programming the LOADER_CTRL register.

This register is documented in the NG-MEDIUM configuration user’s guide.

CMIC Period

The CMIC period can be set by defining parameters used during the bitstream generation.

The CMIC is working on the internal 50 MHz Bitstream manager clock or external provided clock.

CLK in Slave Parallel configuration modes, whose frequency can range from 20 to 50MHz.

Period calculation

CMIC activation is periodic:

(CMIC_DELAY+1)*65536 clk cycles.

CMIC correct multiple ROW at the same time. Each ROW has its own check duration.

Each time an error is corrected in a ROW, the CMIC restart at the beginning of this ROW automatically.

At 50Mhz:

With a minimum CMIC delay configuration, the CMIC is requested to start every 1.3ms.

If the previous scan of a ROW is not done yet, it will wait for the next request to start again.

CMIC ROW duration are:

• ROW1: 3.93ms

• ROW2: 2.40ms

• ROW3: 2.98ms

• ROW4: 2.43ms

• ROW5: 3.93ms

CMICs progress example:

At 20Mhz:

With a minimum CMIC delay configuration, the CMIC is requested to start every 3.25ms.

CMIC ROW duration are:

• ROW1: 9.83ms

• ROW2: 6ms

• ROW3: 7.45ms

• ROW4: 6.08ms

• ROW5: 9.83ms

CMICs progress example:

At 50 MHz:

The minimum period is 5.3 ms (4 ms running + 1.3 ms delay) and the maximum 65 days.

The configuration memory scan takes 4 ms.

The minimum delay setting to launch again the CMIC is 1.3 ms (20 ns x 2**16) and the maximum delay is ~65 days (20 ns x 2**48).

At 20 MHz:

The minimum period is 13.25 ms (10 ms running + 3.25 ms delay) and the maximum 162.5 days.

The configuration memory scan takes 10 ms.

The minimum delay setting to launch again the CMIC is 3.25 ms (50 ns x 2**16) and the maximum delay is ~162,5 days (50 ns x 2**48).

Set configuration

The CMIC period is set by default at the minimum value.

To adjust the time interval between two consecutive CMIC the user needs to program it during bitstream generation.