Introduction
The aim of this document is to explain how to simulate a design dedicated to NanoXplore targets under Questa/Modelsim tools.
The needed minimum version is modelsim 10.6d
Design simulation
Simulation
The user design may include NX primitives with files calling nxpackage as follow in a VHDL file:
library nx; use nx.nxpackage.all;
Consequently, the compilation script must include this package and all primitives architectures.
There is one file per variant so for instance, the file to compile is stored in each release in the following path:
nxmap-<version_number>/share/modelsim/nxLibrary-<variant_name>.vhdp
For instance, for NG-MEDIUM or NG-MEDIUM-EMBEDDED target, with nxmap 22.1.0.1 release, the path is:
nxmap-dbg-22.1.0.1/share/modelsim/nxLibrary-Medium.vhdp
Only components and entities are declared in the clear part.
Architecture models are private and encrypted so.
Hereafter an example of TCL script to compile and simulate a design:
#Compile nx file vlib nx vcom -work nx -2008 nxmap-dbg-22.1.0.1/share/modelsim/nxLibrary-Medium.vhdp #Compile design file vlib work vcom -work work -2008 sub_module1.vhd vcom -work work -2008 sub_module2.vhd vcom -work work -2008 top.vhd #Compile testbench vcom -work work -2008 tb_top.vhd #Simulate vsim -t 1ps -lib work work.tb_top
Netlist simulation
It can be useful to simulate a design with the output netlist generated after synthesis. Indeed, it give the ability to check NXmap synthesis tool mapped correctly the design into a flattened design containing only NX primitives even after optimizations.
Netlist generation
The netlist must be generated using NXmap tool in the NXmap flow as follows:
p.save('<file_name>.<extension>')
Output netlist can be in VHDL or verilog code.
Generate an output netlist after at least synthesizing step 2.
For instance, the netlist can be generated after the final routing step like the following example:
from nxmap import *
#Project creation
p=createProject('')
p.setVariantName("NG-MEDIUM")
p.setTopCellName("work", "top")
p.addFile('work','sub_module1.vhd')
p.addFile('work','sub_module2.vhd')
p.addFile('work','top.vhd.vhd')
#Project steps
p.synthesize()
p.place()
p.route()
p.save('top_routed.vhd')
Simulation
Then, in the simulation script, netlist must be compiled instead of all design files as follows:
#Compile nx file vlib nx vcom -work nx -2008 nxmap-dbg-22.1.0.1/share/modelsim/nxLibrary-Medium.vhdp #Compile design file vlib work vcom -work work -2008 top_routed.vhd #Compile testbench vcom -work work -2008 tb_top.vhd #Simulate vsim -t 1ps -lib work work.tb_top
Backannoted simulation
Backannoted simulation is a simulation with the output netlist but taking account of timing delays between and inside NX primitives.
It can be useful in order to detect a timing violation in the design and it consequence.
Netlist and SDF generation
In addition of the netlist, a Standard Delay Format (SDF) output file must be generated using NXmap tool in the NXmap flow as follows:
p.save('<file_name>.sdf','<conditions>)
Conditions get different voltage and temperature and must be in the following list:
bestcase: -40°C / VDD+10%
typical: 25°C / VDD-10%
worstcase: 125°C / VDD-10%
For instance, the netlist can be generated after the final routing step like the following example:
from nxmap import *
#Project creation
p=createProject('')
p.setVariantName("NG-MEDIUM")
p.setTopCellName("work", "top")
p.addFile('work','sub_module1.vhd')
p.addFile('work','sub_module2.vhd')
p.addFile('work','top.vhd.vhd')
#Project steps
p.synthesize()
p.place()
p.route()
p.save('top_routed.vhd')
p.save('top_routed.sdf','worstcase')
A SDF file described each path with a minimum, a maximum and an optional typical delay time.
NanoXplore SDF file contain only minimum and maximum values so only -sdfmin and -sdfmax arguments are allowed.
Simulation
Instead of the modelsim file, the backannoted file must be compile.
There is one file per variant so for instance, the file to compile is stored in each release in the following path:
nxmap-<version_number>/share/modelsim/nxLibrary-<variant_name>.vhdp
For instance, for NG-MEDIUM or NG-MEDIUM-EMBEDDED target, with nxmap 22.1.0.1 release, the path is:
nxmap-dbg-22.1.0.1/share/backannoted/nxLibrary-Medium.vhdp
Then, in the simulation script, netlist must be compiled instead of all design files and SDF option added linking the top instance in the simulation command as follows:
#Compile nx file vlib nx vcom -work nx -2008 nxmap-dbg-22.1.0.1/share/backannoted/nxLibrary-Medium.vhdp #Compile design file vlib work vcom -work work -2008 top_routed.vhd #Compile testbench vcom -work work -2008 tb_top.vhd #Simulate vsim -t 1ps -lib work work.tb_top -sdfmax sim/:tb_top:i_top_0=top_routed.sdf