NG-MEDIUM NX1H35AS is the first Radiation Hardened By Design (RHBD) SRAM-based FPGA developped by NanoXplore, manufactured on the rad-hard 65nm CMOS technology platform for space applications from ST Microelectronics. The programmable matrix is built on an interconnect architecture made of 4-input Look-up tables with LUT extender to support wider operations, configurable DFF, Coarse Grain Blocks with user configurable memories and Digital Signal Processing units, etc… offering a high logic density.
This page provides a list of all available documentations related to use efficiently the NG-MEDIUM.
Documentation
As a radiation hardened FPGA, the NG-MEDIUM NX1H35AS has been through qualification process for flight applications following the brave rules. The datasheet of the NG-MEDIUM follow the following rules:
SPACE datasheet applies for RHBD qualified component:
FAMILY datasheet applies for RHBD unqualified component : FAMILY NX1H35AS Datasheet
The NG-MEDIUM NX1H35AS is configured by loading the bitstream into internal configuration memory using one of these following programming modes:
JTAG,
Slave Parallel 8 bits,
Slave Parallel 16 bits,
Slave SpaceWire, compliant ECSS-E-ST-50-12C link,
Master SPI, compliant with SPI JESD68.01
The configuration guide documentation described every programming mode with associated features and usages:
The NG-MEDIUM NX1H35AS is assembled in either Ceramic/Hermetic packages for Traditional Space projects as well as Organic package for New Space missions. The package user guide provides detailed description of the Plastic/Ceramic packaging solutions used to assemble the NG-MEDIUM NX1H35AS:
When programming the NG-MEDIUM NX1H35AS, the bitstream loaded into the chip is verified with an integrated scrubber controller named CMIC. The CMIC is the engine that checks the integrity of the configuration memory of the FPGA. The CMIC application note described the role and the key features of this module.
Application notes:
NG-FPGAs offer a very flexible architecture that allows the implementation of a wide range of applications. However, the user must understand that a safe and reproducible behavior can be guaranteed only if some simple but efficient and necessary design rules have been adopted during the design steps. The Cookbook documentation describes HDL rules and digital design methodology to to follow in order to take the best advantage of the NX-FPGAs:
The reliability of the NG-MEDIUM NX1H35AS has been put through intensive radiation campaigns for which results are analyzed into Radiative Tests report:
The complete pinout description for the different packaging used for NG-MEDIUM NX1H35AS are listed in the Pinout document below:
Given specific configuration and context used to program resources of the FPGA matrix, the size of the bitstream generated may vary based on what is used for the application. The Bitstream Size Estimator gives an estimation on which resources will have an impact on the size of the bitstream:
NanoXplore provides characterized data through IBIS models for temperature and corner case conditions aimed for simulation works. Power consumption estimation can be computed using NXPowerEstimator for any project application given which kind and how many resources will be used to map the design:
NG-MEDIUM IBIS model for I/O : ngmedium_io_pad_complex.ibs
NX Power estimator for NG-MEDIUM : NXPowerEstimator_NGMEDIUM_v1d.xlsm
IPs compatible with NG-MEDIUM
NanoXplore is willing to develop internal IPs for NG-Medium use and already work with third-partner providers for some IPs currently available within the NXcore tool, part of the NXmap software chain.