Table of figures

Hierarchy report providing user modules detection

...

Example of path detail table

Copyright

All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.

Introduction

This document is intended to guide users of NanoXplore Impulse software through all the steps involved in the design flow and the options available in NanoXplore design suite:

...

All commands described in this document for NXpython can be applied to the provided VHDL examples in example folder.

Package description

The provided impulse archive contains the following directories:

• bin       folder contains binary files for each supported Linux distribution

• doc      folder contains documentation files in pdf format

• example folder contains several examples of different projects with design sources in VHDL

• lib64 folder contains dynamic libraries and Python modules for each supported Linux distribution and associated Python version

• share folder contains additional files (vhdl libraries, simulation libraries, etc...)

Installation

To install impulse, the user needs to unpack nxdesignsuite-VERSION.tar.gz file into the installation directory (e.g. /opt/NanoXplore) using the following command:

...

Where servername is the hostname of the server running the license daemon and 27000 is the port the daemon listens to.

Run nxpython

To run nxpython, use the following command:

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from nxpython import *

Anchor
nxpythonspec nxpythonspec

Nxpython specification

Command list and context

Heraafter a table of all available nxpython commands and the context they affect:

General commands

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the impulse module.

createProject([workingDirectory])

This method is used to create an empty project object. The project can then be loaded or built.

...

project = createProject("/path/to/working/directory/")

getErrorCount()

This function returns the number of errors issued during Synthesize, Place and Route flow steps.

...

Output:

Errors: 0

getRemarkCount()

This function returns the number of remarks issued during Synthesize, Place and Route flow steps.

...

Output:

Remarks: 10

getWarningCount()

This function returns the number of warnings issued during Synthesize, Place and Route flow steps.

...

Output:

Warnings: 0

listOptions()

This method lists all available options for current project.

...

| Available project options are:
|   +---------------------------------------------------------------------------+
| | Global                                                                                     |
| +-------------------------------+----------+------------------------------+
| |  Autosave                     |      Yes |                       No Yes |
| | +ClearStack                   |       No |                       No Yes |
| |  Dynamic                      |       No |                       No Yes |
| | +InternalReport               |       No |                       No Yes |
| |  MaxRegisterCount             |     2500 |    Value must be an unsigned |
| | +TimingDriven                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 1/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DefaultFSMEncoding           | OneHot   | Binary OneHot OneHotSafe    
                                                            OneHotSafeExtra |
| |  DefaultRAMMapping            |     AUTO |          AUTO RF RAM RAM_ECC |
| |  DefaultROMMapping            |     AUTO |      AUTO LUT RF RAM RAM_ECC |
| |  DisableAssertionChecking     |       No |                       No Yes |
| |  DisableKeepPortOrdering      |       No |                       No Yes |
| |  DisableRAMAlternateForm      |       No |                       No Yes |
| |  DisableROMFullLutRecognition |       No |                       No Yes |
| |  IgnoreRAMFlashClear          |       No |                       No Yes |
| |  ManageUnconnectedOutputs     |    Error |           Error Power Ground |
| |  ManageUnconnectedSignals     |    Error |           Error Power Ground |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 2/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DisableAdderBasicMerge       |       No |                       No Yes |
| |  DisableAdderTreeOptimization |       No |                       No Yes |
| |  DisableAdderTrivialRemoval   |       No |                       No Yes |
| |  DisableDSPAluOperator        |       No |                       No Yes |
| |  DisableDSPFullRecognition    |       No |                       No Yes |
| |  DisableDSPPreOperator        |       No |                       No Yes |
| |  DisableDSPRegisters          |       No |                       No Yes |
| |  DisableLoadAndResetBypass    |       No |                       No Yes |
| |  DisableRAMRegisters          |       No |                       No Yes |
| |  ManageAsynchronousReadPort   |       No |                       No Yes |
| |  ManageUninitializedLoops     |       No |              No Power Ground |
| |  MappingEffort                |     High |              Low Medium High |
| |  OptimizedMux                 |      Yes |                       No Yes |
| | -SynthesizingEffort           |   Medium |              Low Medium High |
| | -UseSynthesisRetiming         |       No |                       No Yes |
| |  VariantAwareSynthesis        |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 1/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  BypassingEffort              |   Medium |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 2/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -SharingEffort                |   Medium |              Low Medium High |
| | -SharingFanout                |      100 |                          100 |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 3/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  CongestionEffort             |     High |              Low Medium High |
| |  DensityEffort                |      Low |              Low Medium High |
| | -PartitioningEffort           |   Medium |              Low Medium High |
| |  RoutingEffort                |   Medium |              Low Medium High |
| | -UnificationEffort            |      Low |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 4/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  PolishingEffort              |     High |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 5/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -DoubleAccess                 |      Yes |                       No Yes |
| | -Permissive                   |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 1/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 2/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 3/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Bitstream                                                               |
| +-------------------------------+----------+------------------------------+
| |  ExhaustiveBitstream          |       No |  No Config Context 
                                                              ConfigContext |
| |  GenerateBitstreamCMIC        |       No |                       No Yes |
| | -MultiBlock                   |       No |                       No Yes |
| |  UnusedPads                   | Floating | Floating WeakPullUp 
                                                               WeakPullDown |
| | -noCfgCtx                     |       No |                       No Yes |
| | -noHeader                     |       No |                       No Yes |
| | -noRun                        |       No |                       No Yes |
| | -noThermalSensor              |       No |                       No Yes |
| | -noWorkaround                 |       No |                       No Yes |
| | -simpleFrames                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+

printError(message)

This function is used to print an error message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by ERROR string so it can be easily found.

...

ERROR	|  It's a trap!

printRemark(message)

This function is used to print a remark message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by REMARK string so it can be easily found.

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REMARK	|  This is a remark

printText([message])

This function is used to print a message in the impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the impulse output.

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| There is no spoon.

printWarning(message)

This function is used to print a warning message in the impulse output. This includes terminal output and log file if set. A warning message is prefixed by WARNING string so it can be easily found.

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WARNING | The cake is a lie.

setCoreCount(core_count)

This function sets the number of core to use in multi-thread algorithm.

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| Setting core count to 2

setDirAutoChange(change_project_dir)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

...

p = createProject()
setDirAutoChange(False)
p.load('my_path/routed-auto.nym')

setLogDirectory(log_directory)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

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| Setting log directory to TestLogDirectory

usage()

This method displays application usage.

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| Usage:
 |   $> nxpython3
 |     will run nxpython3 in interactive mode
 |     
 |   $> nxpython3 file.py
 |     will run the given python file in nxpython3 in batch mode
 |     
 |   options
 |     several options can be used when running nxpython3.
 |     Options must be placed before the file.py argument.
 |     Any option placed after will be passed to the file.py.
 |       -g or -gui        execute nxpython3 with graphical support
 |       -c or -core CORE  execute nxpython3 with maximum core number
 |       -v or -version    display nxpython3 version
 |       -h or -help       display this help

version()

This method displays application version.

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| Copyright (C) 2010-2020, NanoXplore, All rights reserved

Expected expressions for NXpython methods

NxPython methods get a standardized format for arguments expecting a path.

This section describes the expression format specific to NX.

Impacted methods:

The following methods allow regular expressions / wildcard formats in order to match with multiple instances:

...

·       getRegisters

·       setSite

·       …

Maintainability:

It is no longer necessary to escape (with the ‘\’ character) special characters for these methods.

...

However, the old format is still compliant and still operates.

User use:

In a usual way, a copy/paste of a path from a log file works for the constraint.

...

addMappingDirective(getModels(“add_`[1-2][0-9]`u_*”), …)

Project related methods

This section presents the methods related to the project object.

addADCLocation(name, location)

This method is used to place an ADC in a specific location

...

project.addADCLocation('WRAPPER_0|ADC_0','ADC1')

addBank(name, dict)

The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.

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project.addBank('IOB0', {'voltage': '2.5'})

addBanks(dict)

The method addBanks allows user to configure several banks of the FPGA to be used for configuration of inputs/outputs of the HDL module. addBanks use a dictionary as an argument.

...

ioBanks = { 'IOB0'  : {'voltage': '2.5'}
                  , 'IOB1'  : {'voltage': '2.5'}
                  , 'IOB2'  : {'voltage': '2.5'}
                  , 'IOB3'  : {'voltage': '2.5'}
                  , 'IOB4'  : {'voltage': '2.5'}
                  , 'IOB5'  : {'voltage': '2.5'}
                  , 'IOB6'  : {'voltage': '2.5'}
                  , 'IOB7'  : {'voltage': '2.5'}
                  , 'IOB8'  : {'voltage': '2.5'}
                  , 'IOB9'  : {'voltage': '2.5'}
                  , 'IOB10' : {'voltage': '2.5'}
                  , 'IOB11' : {'voltage': '2.5'}
                  , 'IOB12' : {'voltage': '2.5'}
          }
project.addBanks(ioBanks)

addBlackBox(name, type, mapping, interface)

The method addBlackBox allows users to define customized mapping of certain HDL modules on the specific FPGA blocks and to dispose the interface of the blocks.

...

project.addBlackBox('myMicroCode', 'ROM', 'RF', 'AD(addr),DO(micro),CK(clk)')

addBlackBox() : for Preplaced IP

The idea is to offer the possibility to the user to reuse the result of an impulse flow as an IP in a top design.

...

The user can then reuse the result of this first flow in another design. named top, which instanciates the IP entity several times.

...

To specify that an entity of the design top must be taken into account as a preplaced IP, the user has to add the following constraint before the synthesis

...

Among the instances of the ring, some are not supported yet :
PLL, WFG, CR5, SOC_IF, HSSL

addDACLocation(name, location)

This method is used to place a DAC in a specific location

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project.addDACLocation('WRAPPER_0|DAC_0','DAC1')

addFalsePath(from_list, to_list)

This method is used to specify the false path for the timing paths. This constraint is used by timing driver algorithms and static timing analysis.

...

addFile([library], file)

This method is used to add a HDL source file to the project. The file can be added to a specific library by passing its name as the first optional library argument. The default library is work.

...

project.addFile('src/simple.vhd')
project.addFile('src/complex.vhd:VHDL_93')
project.addFile('src/simple_verilog.v:VERILOG_95')
or
project.addFile('myLib', 'src/simple.vhd')

addFiles([library], fileList)

This method is used to add several HDL source files to the project. The files can be added to a specific library by passing its name as the first optional library argument. The default library is work.

...

addHSSLLocation(pattern,location)

This method is used to set the spot in which a HSSL should be set.

...

project.addHSSLLocation('i_hssl_esistream|i_HSSL_ONLY|i_NX_HSSL_FULL|ctrl', 'HSSL2')

addMappingDirective(name, type, mapping)

This method is used to add a mapping directive for Synthesis flow step which overrides the default nxpython mapping behavior for a specific HDL module or instance.

...

Example:

If the HDL design named myTest contains a small 3 write ports and 3 read ports FIFO named myFifo, nxpython cannot automatically map it into RF or RAM, but user can add a mapping directive to map it into DFF:

...

addMaxDelayPath(from_list, to_list, delay)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

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project = createProject()
project.load('routed.nym')
project.addMaxDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                        getRegister('UUT2|dout_reg[61]'), 3900)

addMemoryInitialization(name, type, file)

This method is used to specify a file that will be used to initialize a specific memory instance.
Arguments:

...

0000
1000
100
10
1

addMinDelayPath(from_list, to_list, delay)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

...

project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'),
                                     getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1200)

Anchor
addmodule addmodule

addModule(model, instance, format)

This method is used to add a HDL module definition to the current project that contains all HDL logic elements including within the model given in argument.

...

nxpython reports user modules detection in the hierarchy.rpt (previous figure) file with detailed information including resources used for each module and detailed hierarchy of all modules defined in the current project.

...

addMulticyclePath(from_list, to_list, cycle_count)

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

...

addObstruction(name, column, row, width, height)

This method is used to create an obstruction object which will be removed from impulse resources for Place & Route steps.

...

project = createProject()
project.load('synthesize.nym')
project.addObstruction('obstr', 10, 2, 15, 5)

Anchor
addpad addpad

addPad(name, parameters)

This method allows user to configure an input/output of the HDL module into specific pad of the FPGA. For the given pad, the configuration has two basic argument (name and parameters).

...

...

Unit of inputSignalSlope key is V/ns in the range [0.5;20] (Default 0).

...

#LVDS implementation
project.addPad( 'spw_rxd[0]' : {'location': 'IOB19_D16P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT', 'turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_rxs[0]' : {'location': 'IOB19_D17P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT','turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_txd[0]' : {'location': 'IOB19_D14P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})
project.addPad( 'spw_txs[0]' : {'location': 'IOB19_D15P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})

addPads(pads)

This method is used to configure inputs/outputs of the HDL module into specific pads of the FPGA. The argument is a dictionary that associates the HDL input/output name to a dictionary, which can contain some keys (location, type, weakTermination, slewRate, termination, inputDelayLine, outputDelayLine, differential, terminationReference, turbo) as defined in addPad(name, parameters).

...

addPin(name, location)

This method allow user to configure an input/output of the HDL module into specific pin of the embedded FPGA. This method is reserved to embedded variants of FPGA.

...

project.addPin('A', 'TUI200')

addPins(pins)

This method allow user to configure inputs/outputs of the HDL module into specific pins of the embedded FPGA. This method is reserved to embedded variants of FPGA.

...

pins = {
	  'A': 'TUI200',
	 'B': 'TUI201'
          }
project.addPins(pins)

Anchor
addparam addparam

addParameter(name, value)

This method allows user to specify the value of the top design generic parameters.

...

Anchor
addparameters addparameters

addParameters(parameters)

In case of a large number of parameters, a parameter dictionary can be created consisting of the name of the parameter as a key and its respective value. Both name and value must be string.

...

addPLLLocation(pattern, location)

This method is used to set the spot in which a PLL should be set.

...

#placing pll0, pll1, pll2, pll3 in different CKGs
project.addPLLLocation('pll0', 'CKG1.PLL1')
project.addPLLLocation('pll1', 'CKG2.PLL1')
project.addPLLLocation('pll2', 'CKG3.PLL1')
project.addPLLLocation('pll3', 'CKG4.PLL1')
#placing a PLL located in a sub-hierarchy of the design
project.addPLLLocation('FIR_MF|CLKG|PLL_20_160', 'CKG4.PLL1')

Anchor
addregion addregion

addRegion(name, column, row, width, height, exclusive)

This method is used to create a region among the FPGA resources where HDL elements will be placed during Place step.

...

project = createProject()
p.addRegion('ALU',      13, 6, 14, 6)
p.addRegion('REGISTER', 22, 6, 23, 6, True)

addRingLocation(name, location)

This method is used to place an instance in the I/O ring of the FPGA. addRingLocation can be used instead of addPLLLocation, addWFGLocation or addPin.

...

project.addRingLocation('PLL0','CKG1.PLL1')
project.addRingLocation('WFG_3','CKG4.WFG_C1')

addRingLocations(dictionary)

In case of a large number of instances to be placed in the I/O Ring, a dictionary can be created consisting in the name of the instance as a key and its association location. Both name and location must be string.

...

rings = { 'PLL0' : 'CKG1.PLL1', 
               'PLL1' : 'CKG2.PLL1',
               'WFG_0' : 'CKG1.WFG_C1',
               'WFG_1' : 'CKG2.WFG_C1' }
project.addRingLocations(rings)

addVerilogIncludeDirectory(directory)

This method is used to add an extra directory containing Verilog files to the project. This is used when the included files are external to the working directory.

...

project.addVerilogIncludeDirectory('include’)
or
project.addVerilogIncludeDirectory('../lib’)

addVerilogIncludeDirectories(directoryList)

This method is used to add several extra directories containing Verilog files to the project. This is used when the included files are external to the working directory.

...

project.addVerilogIncludeDirectories(['include’, ‘../lib’])

addVlogDefine(name,value)

This method is used to add a parameter definition for Verilog files.

...

project.addVlogDefine('G_DATA_SIZE’,'8')

addVlogDefines(dictionnary)

This method is used to add parameters definition for Verilog files.

...

project.addVlogDefines({'G_DATA_SIZE’:'8','G_ADDR_SIZE’:'16'})

addWFGLocation(name, location)

This method is used to set the spot in which a WFG should be set.

...

project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)

...

importSdcFile(filePath)

This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.

...

project.applySdcFileimportSdcFile(./sdc_directory/constraints.sdc)

clearBanks()

clearBanks() method remove all bank specification previously added in the project.

...

project = createProject()
project.addBank('IOB0', {'voltage': '2.5'})
project.clearBanks()

clearFabricPrePlaceConstraints(regionName)

Clears all preplacing constraints for fabric elements. It removes the impact of the setSite constraint:

...

project = createProject()
project.setSite('i_cpt_0|s_cpt_out_reg[0]', 'TILE[3x2]')
project.clearFabricPreplacedConstraints()
project.setSite('i_cpt_0|s_cpt_out_reg[0]', 'TILE[4x2]')

clearPLLs()

clearPLLs() method remove specification and location for PLLs previously added in the project.

...

project = createProject()
project.addPLLLocation('pll_0', 'CKG2.PLL1')
project.clearPLLs()

clearPads()

clearPads() method remove all inputs/outputs of the HDL module previously configured into specific pads of the FPGA.

...

project = createProject()
pads = {
	'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination': 'PullUp', 
          'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 'differential': False, 
         'turbo': True}
project.addPads(pads))
project.clearPads()

clearPins()

clearPins() method remove all inputs/outputs of the HDL module previously configured into specific pins of the embedded FPGA

...

project = createProject()
pins = {
	'A': 'TUI200',
	'B': 'TUI201'
          }
project.addPins(pins)
project.clearPins()

clearWFGs()

clearWFGs() method remove specification and location for WFGs previously added in the project.

...

project = createProject()
project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)
project.clearWFGs()

Anchor
confinemodule confinemodule

confineModule(name, region)

This method allows to confine a module into a user defined region of the FPGA.

...

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a HDL module into a specific region. The aim of constrainModule is to provide a unique and simple function to perform the whole region driven flow described in Creating and handling regions section.

...

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a virtual module into a specific region. The aim of this function is to identify source and destination registers in order for all logic elements (LUT, carry) between these registers to be placed into a region created with the regionName argument.

...

createAnalyzer

If a targeted design is already routed, user can launch static timing analysis by creating a timing analyzer.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createAnalyzer()

createClock(target, name, period, [rising, falling])

This method is used to create a clock constraint of a timing point. This constraint is used by timing driver algorithms and static timing analysis.

...

In the example above, to define a clock with 100MHz for net "Clk", the following three commands are equivalent:

project = createProject()
project.load('routed.nym')
project.createClock(getRegisterClock(reg1'), 'clk', 10000)
or
project.createClock(getPort(Clk'), 'clk', 10000)
or
project.createClock(getClockNet('Clk'), 'clk', 10000, 0, 5000)

createGeneratedClock(source, target, name, relationship)

This method is used to create an internally generated clock constraint at a timing point. This constraint is used by timing driver algorithms and static timing analysis.

...

...

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But noted that the "clk_reg" is driven by falling edge of master clock, the relation between the master clock and generated clock is the following:

project = createProject()
project.load('routed.nym')
project.createClock(getPort('Clk'), 'Clk', 10000)
or
project.createGeneratedClock(getRegisterClock('clk_reg'),getRegisterClock('reg2'), 'clk1', {'DivideBy': 2})
or
project.createGeneratedClock(getClock('Clk'),getRegisterClock('reg2'), 'clk1', {'Edges': [2, 4, 6]})

...

createSimulator()

This method is used to create a simulator object. A simulator object is used to simulate the project with a specified testbench.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createSimulator()

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'),getRegister('data_reg[0]'), 'clk1_div2', {'DivideBy': 2})

destroy() (project)

This method is used to destroy the project.

...

Display after destruction
Traceback (most recent call last):
    File "test.py", line 22, in <module>
        project.display()
impulse.error: Invalid Request: Obsolete object

destroy() (analyzer)

This method is used to destroy the analyzer.

This method takes no argument.

Example:

a = project.createAnalyzer()
a.launch()
a.destroy()

display()

This method is used to open current project in impulse graphic user interface. It can be called several times from the same Python script.

...

exportAsIPCore(file, options)

This method is used to export the synthesized design to an IPCore. An IPCOre is a HDL description (at NX components level) that can be given as part of new source design to impulse.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/native.nym')
options = { ‘coreName’: ‘IPCore’, ‘encrypt’: ‘All’ }
p.exportAsIPCore(‘IPCore.vhd’, options)
p.synthesize()

exportPlacement([filename])

This method is used to export all placement constraints in order to be re-imported.

Example:

project.exportPlacement()

exportRegions()

This method is used to export all constrainModule constraints in the console. It can be useful if the user modified the region location or size and want to get new constraints to copy them in the script.

...

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3)
project.exportRegions()

exportSites(projectVariable,fileName)

This method is used to export all setSite constraints in a file. It can be useful in order to keep all TILE locations.

...

project.exportSites('p','site_constraints.py')

Anchor
generatebitstream generatebitstream

generateBitstream(file)

This method is used to save the bitstream configuration file to disk. The extension of the target file must be .nxb

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.generateBitstream('bitstream.nxb')

generateSTANetlist(filePath,condition)

This method is used to generate routed netlist and SDF file.

...

project.route()
project.generateSTANetlist(./output_files/routed_sta_file)

setDeviceID(id)

This method is used to change the Device ID in the bitstream header before generating it.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
p.setDeviceID(10) #Set Device ID to 0xA
project.generateBitstream('bitstream.nxb')

getAnalyzer()

This method returns the current analyzer associated to the project to manage STA.

...

project = createProject()
a = project.createAnalyzer()
project.getAnalyzer().launch()

getDirectory()

This method returns the project current directory. This directory is used as root for all relative paths passed as argument of generic functions and/or methods. The default value of the directory is the current working directory.

...

project = createProject()
directory = project.getDirectory()

getHierInfo()

This method returns the detailed hierarchy into a dictionary variable.

...

project = createProject()
hierarchy = project.getHierInfo()
printText(hierarchy)

getLowskewSignals(ignoreTop, showCandidates)

This method is used to get lowskew signals or potential candidates to be lowskew signals. It gives a table of impacted lobes for each lowskew signal

...

getProject()

This method returns the project object.

...

createProject()
project = getproject()

getTimingUnit()

This method returns the timing unit used in STA.

...

printText(project.getTimingUnit())

getTopCellName()

This method returns the name of the top HDL module. If the HDL module is defined inside a library, the name is prefixed by the name of the library followed by a # character.

...

Output:

myLib#simple

getVariantName()

This method returns the variant of the project. The default value of the variant is 'NG-MEDIUM'.

...

Output:

NG-MEDIUM

importPlacement([filename], [regions], [modules], [importAll])

This method is used to re-import exported placement constraints.

...

project.importPlacement('my_placement_constraints.json',['REGION_0','REGION_1'],['MODULE_2_1', 'MODULE_3_2'],True)

initRegister(command, value)

This method is used to write in registers during the generation of bitstream.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.initRegister('SPI_CTRL', '0x01f4003f')
project.generateBitstream('bitstream.nxb')

...

injectLowskew(signal, [lobes])

This method is used to limit inject a lowskew signal to be used in only signal in lowskew network in specified lobes.

Arguments:

...

Example:

project.limitLowskewinjectLowskew('clk')
project.injectLowskew('clk_right','Rx1,Rx2,Rx3,Rx4')

listAvailableLocations(name)

This method is used to print all available pads for a bank or for all banks of a variant .

...

project.listAvailableLocations()
project.listAvailableLocations('IOB10')

load(file)

This method is used to load a previously saved project from disk. The input format (file extension) must be .nym (impulse archive).

...

project = createProject('/home/user/example/vhdl/simple')
project.load('synthesized.nym')

Anchor
modifyaperture modifyaperture

modifyAperture(column, row, width, height)

This method is used to define the size of aperture. The default size value is bounded to the Fabric dimensions.

...

project = createProject()
project.load('synthesize.nym')
project.modifyAperture(10, 2, 15, 5)

modifyObstruction(name, column, row, width, height, exclusive)

This method is used to modify the location or the size of an existed region.

...

project.addObstruction('OBSTR_0', 10, 8, 10, 2)
project.modifyObstruction('OBSTR_0', 10, 8, 10, 3)

place()

modifyPad(name, parameters)

This method is used to modify the configuration of an existed pad.

...

project.addPad('output[0]',{'location':'IOB10D09P', 'standard': 'LVCMOS', 'drive' :'2mA', 'slewRate':'Slow'})
project.modifyPad('output[0]',{'drive' :'16mA', 'slewRate':'Fast'})

modifyRegion(name, column, row, width, height, exclusive)

This method is used to modify the location or the size of an existed region.

...

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3)

place()

This method is used to run the place algorithm on a project.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.setOption('TimingDriven', 'Yes')
project.place()

printHierInfo()

This method prints the detailed hierarchy of a project with the module matched and all instances per module.

...

project = createProject()
project.progress('Synthesize', 3)
project.printHierInfo()

progress(step, number)

This method allows to progress through project to a given flow step.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.progress('Place', 3)

rejectLowskew(signal)

This method avoids local lowskew signal to be converted in global lowskew signal.

...

project.rejctLowskew('sub_module0|local_reset')

removeFile(libName, filePath)

This method allows to remove a file from a project.

...

project.addFile('work','sub_modul_0.vhd')
project.addFile('work','sub_modul_1.vhd')
project.removeFile('work','sub_modul_0.vhd')
project.removeFile(sub_modul_1.vhd')

removeFiles()

This method allows to remove files from a project.

...

project.addFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])
project.removeFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])

removeObstruction(name)

This method is used to destroy a given obstruction object.

...

project.addObstruction('obstr', 10, 2, 15, 5)
project.removeObstruction('obstr')

removeRegion(name)

This method is used to destroy a given region.

...

project.addRegion('CNTRL',     4, 6,  2, 1)
project.removeRegion('CNTRL')

removeSoftModules(libName, fileList)

This method allows to remove all HDL soft modules from a project.

...

reportDesignComplexity(html_file)

This method reports the design complexity, clock domain by clock domain, indicating the logic depth for all paths of the design and illustrates it with a chart in HTML format:

...

The output HTML file looks like:

 reportHierarchyComplexity()

...

project.reportHierarchyComplexity()

Anchor
reportinstances reportinstances

reportInstances()

This method reports the instances utilization of the programmed design on the current variant. Three tables are printed. The first one contains values for all types of instances. The instances are grouped by categories:

...

reportLowskewSignals(logfile)

This method reports the lowskew signals:

...

project.reportLowskewSignals('lowskew_report')

Anchor
reportports reportports

reportPorts()

This method reports the ports found in HDL source and the ones manually added by user in the project. The report displays the following information:

...

project = createProject()
project.load('/home/user/example/vhdl/simple/placed.nym')
project.reportPorts()

Anchor
reportregions reportregions

reportRegions()

This method reports occupied resources by HDL elements within every region created in the FPGA.

...

resetTimingConstraints()

This method is used to reset all timing constraints for current project.

...

project = createProject()
project.load('/home/user/simple/routed.nym')
project.resetTimingConstraints()

Anchor
route route

route()

This method is used to run the route algorithm on a project.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/placed.nym')
project.setOption('TimingDriven', 'Yes')
project.route()

Anchor
savefile savefile

save(file,conditions)

This method is used to save the current project into a impulse archive (.nym), a design netlist (.v or .vhd) or to generate a sdf file containing delays of the design supporting bestcase, worstcase and typical scenarios.

...

project = createProject()
project.load('native.nym')
project.synthesize()
project.save('synthesized.nym')
project.save('synthesized.vhd')
project.route()
project.save(‘routed.vhd’)
project.save('sdf_file_bestcase.sdf','bestcase') #generate a sdf file defining bestcase scenario
project.save('sdf_file_worstcase.sdf','worstcase') #generate a sdf file defining worstcase scenario
project.save('sdf_file_typical.sdf','typical') #generate a sdf file defining typical scenario
project.save(‘routed.sdf’)

setAnalysisConditions(conditions)

This method is used to specify the chip conditions for static timing analysis.

...

project.setAnalysisConditions(WorstCase)

setCaseAnalysis(value, net_list)

This method is used to specify a constant logic value to the given tests.

...

setClockGroup(group1_list, group2_list, option)

This method is used to specify which clocks are not related. This constraint is used by timing driver algorithms and static timing analysis. 

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet(CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet(CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'),getClock('clk2'), 'exclusive')

setDescription(description)

This method is used to set a description to a project.

...

project = createProject()
project.setDescription('Impulse project for training')

setDirectory(directory)

This method is used to change project directory.

...

project = createProject()
project.setDirectory('./new_dir')

Anchor
setfocus setfocus

setFocus(column, row)

This method is used to specify the position of the focus.

...

project = createProject()
project.load('synthesize.nym')
project.setFocus(4, 4)

setGCKCount(count)

This method is used to limit the number of GCK at the end of Placing step 2.

...

project.setGCKCount(20)

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500,getPort('RST'))

Anchor
setoption setoption

setOption(name, value)

This method is used to set the value of a nxpython option. An option can be set at any time of the design flow.

...

“00”, “01”, “10”

“001”, “010”, “100”

...

project.setOption('MappingEffort', 'Medium')

setOptions(options)

This method allows user to set the values of several nxpython options. The options can be set at any time of the design flow.

...

options = {
	'MappingEffort': 'Medium',
	'AdderToDSPMapThreshold': '12'
}
project.setOptions(options)

setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

This method specifies the data arrival times at the specified output ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setOutputDelay(getClock('CLK'), 'rise', 1000, 1500, getPorts('dataout[`[0−5]`]'))

setSite(instancePattern, siteName)

This method is used to place a fabric instances into a specific TILE/CGB site.

...

p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]')#DFF
p.setSite('i_cpt_1|LessThan_L23/lut_0','TILE[5x2]')#LUT
p.setSite('i_cpt_2|add_L24_stage1','TILE[7x2]')#CY
p.setSite('i_RAM_small|s_mem*','TILE[11x2]')#RF
p.setSite('i_RAM_big|s_mem*','TILE[11x4]')#RAM
p.setSite(i_cpt_3|add_L24*','CGB[9x4]:L')#DSP

setTopCellName([library], name)

This method is used to set the name of the HDL top module. If the HDL module is defined inside a library, the name of the library can be passed as the first argument.

...

setVariantName(variant)

This method is used to set the variant of the project. The default value of the variant is 'NG-MEDIUM'.

...

project = createProject()
project.setVariantName('NG−MEDIUM')
project.setVariantName('NG−LARGE')
project.setVariantName('NG−ULTRA')

Anchor
synthesizef synthesizef

synthesize()

This method is used to synthesize the HDL source files and realize the technology mapping against nxpython library.

...

project = createProject()
project.load('native.nym')
project.synthesize()

Simulation related methods

This section presents the methods of the simulator object. This object controls the simulation of the design.

addTestBench([library], testBench)

This method is used to add a testBench file. The file can be added to a specific library by passing its name as the first optional argument 'library'. The default library is 'work'.

...

simulator.addTestBench(‘testbench.vhd’)
or
simulator.addTestBench(‘myLib’, ‘testbench.vhd’)

addTestBenchs([library], fileList)

This method is used to add several testbench files. The files can be added to a specific library by passing its name as the first optional argument library. The default library is work.

...

simulator.addTestBenchs([‘testbench1.vhd’, ‘testbench2.vhd’])
or
simulator.addTestBenchs(‘myLib’, [‘testbench1.vhd’, ‘testbench2.vhd’])

addWave(wave)

This method is used to add a signal which will be displayed in vsim. It is also possible to add all the available waves by passing '*' as argument.

...

simulator.addWave(‘*’)
or
simulator.addWave(‘A’)

addWaves(wavelist)

This method is used to add several signals which will be displayed in vsim.

...

simulator.addWaves([‘A’, ‘B’, ‘O’])

destroy()

This method is used to destroy the simulator object.

...

simulator.destroy()

launch(graphical)

This method is used to run the simulation.

To run the simulation, the simulator object must be fully initialized. You must at least have specified the testbench files and the testbench top cell.tim

The simulation is launched on a netlist representing the current state of the project.

...

project = createProject()
project.load(‘routed.nym’)
simulator = project.createSimulator()
simulator.setTestBenchTop(‘testbench’)
simulator.addTestBench(‘testbench.vhd’)
simulator.launch(True)

setDuration(duration)

This method is used to set length in time of the simulation. If not specified (or set to ‘’), vsim will be launched with run -all.

...

simulator.setDuration(‘250ns’)

setTestBenchTop(testBenchTop)

This method is used to set the top cell name of the testbench.

...

simulator.setTestBenchTop(‘testbench’)

setWorkingDirectory(workingDirectory)

This method is used to set the working directory of the simulation

...

simulator.setWorkingDirectory(‘simulation’)

Argument related methods

getClock(clock_name)

This argument method is used to get the clock from a given clock name. A valid clock should be a clock created by command createClock.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'), getClock('clk2'), 'exclusive')

getClockNet(clock_net_name)

This argument method is used to get the net from a given clock net name. It is used by createClock method to specify a clock related point as argument.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)

getClocks(clock_name_expression)

This argument method is used to get the clocks from a given clock name expression. A valid clock should be a clock created by command createClock.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.createClock(getClockNet('CLOCK[3]'), 'test_clkA', 5000, 0, 2000)
project.createClock(getClockNet('CLOCK[4]'), 'test_clkB', 5000, 0, 2000)
project.setClockGroup(getClocks('clk*'), getClocks('test_clk*'), 'exclusive')
project.setClockGroup(getClocks('clk[1-2]'), getClocks('test_clk`[AB]`'), 'exclusive')

getInstances(intance_name)

This argument method is used to get the instances from an instance name. It can be used by some nxpython methods (addMappingDirective, addMemoryInitialization).

...

getModels(model_name)

This argument method is used to get the models from a model name. It can be used by some nxpython methods (addMappingDirective, addMemoryInitialization).

...

getPort(port_name)

This argument method is used to get the port from a given port name. Some nxpython methods need a port as argument.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500, getPort('RST'))

getPorts(port_name_expression)

This argument method is used to get the ports from a given port name expression. Some nxpython methods need a list of ports as argument.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setOutputDelay(getClock('CLK'), 'rise', 1000, 1500, getPorts('dataout[`[0−5]`]'))

getRegister(register_name)

This argument method is used to get the register from a given register name. Some nxpython methods need a register as argument.

...

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
		              getRegister('UUT2|dout_reg[61]'))

getRegisterClock(register_name)

This argument method is used to get the register clock from a given register name. Some nxpython methods need a clock as argument.

...

project = createProject()
project.load('routed.nym')
project.createClock(getRegisterClock('reg1'), 'clk', 10000)

getRegisters(register_name_expression)

This argument method is used to get the registers from a given register name expression. Some nxpython methods need a list of registers as argument.

...

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegisters('UUT1|Gen_seq[3].seq_i|temp_reg[`[0-9]`]'),
		               getRegister('UUT2|dout_reg[61]'))

getRegistersByClock(clock_name)

This argument method is used to get all the registers from the same clock domain. Clock must be created before.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('clk1'),'clk1',20000,0,15000)
project.addFalsePath(getRegistersByClock('clk1'), getRegister('UUT2|dout_reg[61]'))

getWFGOutput(wfg_name)

This argument method is used to get the wfg clock from a given wfg name. Some nxpython methods need a clock as argument.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'), getRegister('data_reg[0]'), 'clk1_div2', 				                 
                             {'DivideBy': 2})

Full script example:

This chapter presents the full Python script of the provided VHDL 'simple' example.

...

import os
import sys
from nxpython import *

dir = os.path.dirname(os.path.realpath(__file__))
project = createProject(dir)
project.setVariantName('NG-MEDIUM')
project.setTopCellName('WOB_MAC_FIR')

project.addFiles([
   'src/src_WOBUL/SUB_ADD.vhd', 
   'src/src_WOBUL/SIN_TAB_8K.vhd', 
   'src/src_WOBUL/SIN_TAB_8K_360.vhd', 
   'src/src_WOBUL/WOBUL.vhd', 
   ])

project.addFiles([
   'src/src_MAC_FIR/MULTI_MAC_FIR_Package.vhd', 
   'src/src_MAC_FIR/CLKGEN.vhd', 
   'src/src_MAC_FIR/SRL_MEM_SYMMETRY_EVEN.vhd', 
   'src/src_MAC_FIR/SRL_MEM_SYMMETRY_ODD.vhd', 
   'src/src_MAC_FIR/TOP_SRL_MEM_MULTI_SYMMETRY.vhd', 
   'src/src_MAC_FIR/MAC_CAPT.vhd', 
   'src/src_MAC_FIR/ADDER_TREE.vhd', 
   'src/src_MAC_FIR/TOP_MAC_FIR.vhd', 
   ])

project.setOptions({
   'MappingEffort': 'High', #can be replaced by  'Medium' or  'Low'
   })

ioBanks = { 
   'IOB12'  : {'voltage': '2.5'},
   'IOB10'  : {'voltage': '1.8'},
   'IOB01'  : {'voltage': '2.5'},
   'IOB00'  : {'voltage': '2.5'},
     }

pads = {
      'CLK25M_IN'  : {'location': 'IOB12_D09P', 'standard': 'LVCMOS', 'drive' :'4mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'RST_PIN'    : {'location': 'IOB10_D12N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},          
      'TRIG_IMMEDIATE_EXT'  : {'location': 'IOB10_D07N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1}, 

      'LEDS_N_8'       : {'location': 'IOB01_D02N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[2]'  : {'location': 'IOB01_D06P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[1]'  : {'location': 'IOB01_D06N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[0]'  : {'location': 'IOB01_D05P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},

      'LEDS_N_4'  : {'location': 'IOB01_D05N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_3'  : {'location': 'IOB00_D03P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_2'  : {'location': 'IOB00_D03N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_1'  : {'location': 'IOB00_D01P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
   }
project.addPads(pads)

#clock constraint
project.createClock(getClockNet('CLK25M_IN'), 'CLK25M_IN', 40000, 0, 20000)

#Create regions ton confine logic
project.addModule('*WOBUL', 'WOBU', 'WOBU-%')
project.addRegion('WOBUR', 1, 2,  2, 4, False)
project.confineModule('WOBU-1', 'WOBUR')

project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[[1-8]].OTHE.OTH_EVEN', 'OTH_EVEN-%')
project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[0].FIRST.FIRST_EVEN', 'FIRST_EVEN-%')
project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[9].CENT.CENTER_EVEN', 'CENTER_EVEN-%')

project.addRegion('OTH_EV_1_R', 2, 10, 1, 1, False)
project.confineModule('OTH_EVEN-1', 'OTH_EV_1_R')
project.addRegion('OTH_EV_2_R', 3, 10, 1, 1, False)
project.confineModule('OTH_EVEN-2', 'OTH_EV_2_R')
project.addRegion('OTH_EV_3_R', 4, 10, 1, 1, False)
project.confineModule('OTH_EVEN-3', 'OTH_EV_3_R')
project.addRegion('OTH_EV_4_R', 5, 10, 1, 1, False)
project.confineModule('OTH_EVEN-4', 'OTH_EV_4_R')

project.addRegion('OTH_EV_5_R', 6, 10, 1, 1, False)
project.confineModule('OTH_EVEN-5', 'OTH_EV_5_R')
project.addRegion('OTH_EV_6_R', 7, 10, 1, 1, False)
project.confineModule('OTH_EVEN-6', 'OTH_EV_6_R')
project.addRegion('OTH_EV_7_R', 8, 10, 1, 1, False)
project.confineModule('OTH_EVEN-7', 'OTH_EV_7_R')
project.addRegion('OTH_EV_8_R', 9, 10, 1, 1, False)
project.confineModule('OTH_EVEN-8', 'OTH_EV_8_R')
project.addRegion('FIRST_EV_1_R', 1, 10, 1, 1, False)
project.confineModule('FIRST_EVEN-1', 'FIRST_EV_1_R')
project.addRegion('CENT_EV_R', 10, 10, 1, 1, False)
project.confineModule('CENTER_EVEN-1', 'CENT_EV_R')

# Synth                 FIR_MF_GEN_DSP_0_DSP_G_INST_DSP_DSP_INST
# Routed              FIR_MF_GEN_DSP_0_DSP_G_INST_DSP_DSP_INST
# Impulse GUI      FIR_MF|GEN_DSP_0_DSP|G_INST.DSP|DSP_INST

#false paths declarations
#project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[*'), getRegisters('FIR_MF|SUM|PRESUM_reg[*'))
#project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][*'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][0]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][1]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][2]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][2]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][4]'))

project.save('native.nym')               
                                         
if not project.synthesize():             
    sys.exit(1)                                                               
project.save('WMFS_Cores_synth.vhd')        
            
if not project.place():                  
    sys.exit(1)                          
project.save('WMFS_Cores_placed.nym')                                         

if not project.route():                  
    sys.exit(1)                          
                                         
project.reportPorts()                    
project.reportInstances()                
                                                                                     
project.save('WMFS_Cores_routed.nym')
project.save('WMFS_Cores_routed.vhd')

analyzer = project.createAnalyzer()
analyzer.launch({
   'conditions': 'worstcase',           # 'typical', 'worstcase', or 'bestcase'
#   'maximumSlack': 10000,
   'searchPathsLimit': 100
   }) 

#bitstream generation
project.generateBitstream('WMFS_Cores.nxb')

print( 'Errors: ', getErrorCount())
print( 'Warnings: ', getWarningCount())

Timing Analysis

Timing path

Timing path is the connection between two certain nodes in the design i.e. connection between primary input and output ports, connection between primary input ports/clock pins and data input pins of the sequential elements, and connection between intermediate clock pins and primary output ports.

Data delay

In impulse, data delay is the delay of a timing path. For example, the delay between the launch edge of the clock at the source register and data input pin of the destination register. In following picture, the path for the data delay between source register DFF1 and destination register DFF2 is shown in blue.

...

Clock skew

Clock skew is the difference between the latch clock delay at the destination register and launch clock delay at the source register. Considering the example shown in previous figure, clock skew is calculated as follows:

clock skew = Clock delay at DFF2 − Clock delay at DFF1

Setup/Hold time

Setup time is the minimum amount of time required for a signal to be held stable before the clock transition.

Hold time is the minimum amount of time required for a signal to retain its value after the clock transition. In impulse, the analysis of setup/hold time is performed in order to calculate the data arrival time which will be explained shortly.

Recovery/Removal time

Recovery time is the minimum amount of time required for an asynchronous control signal to be held stable after its de-assertion before the next active clock edge. The recovery time calculation corresponds to the setup time calculation but for the asynchronous control signals i.e. reset.

...

Similarly, removal time is the minimum amount of time for an asynchronous signal to be held stable before its de-assertion after the previous active clock edge. The removal time calculation corresponds to the hold time calculation but for the asynchronous signals.

Timing domain

In impulse, the term ‘domain’ is used to define a group of certain timing paths. As mentioned earlier, the timing paths include the connection between primary input and output ports, connection between primary input ports/clock pins and data input pins of the sequential elements, and connection between intermediate clock pins and primary output ports.

...

            For example in following figure, three domains D1, D2 and D3 are shown between input and clock "clk" (D1: input to clk), between clock "clk" of source registers and clock "clk" of destination registers (D2: clk to clk), and between clock "clk" and output (D3: clk to output) respectively.

...

Data arrival time

In impulse, data arrival time includes the overall data delay, clock skew and setup/hold time (recovery/removal) for a critical timing path in a domain. Based on the setup/hold verification, data arrival time can be either maximum or minimum. In both cases, data arrival time is calculated as follows:

Maximum data arrival time =
       max{∀(path delay = data delay − clock skew + setup or recovery) : path ∈ domain}
Minimum data arrival time =
       min{∀(path delay = data delay − clock skew − hold or removal) : path ∈ domain}

Setup/Recovery, Hold/Removal time relationship

The transfer of data signal from one sequential element to another requires certain timing checks for correct functionality. It involves hold and setup time verification with respect to launch and latch edge of the clock at the source and destination sequential element respectively.

...

Between launch and latch clock, hold and setup time relationship is established which it is essentially the delay between the active edges of these clocks. This relationship is then used to determine positive or negative slack, validating the timing characteristics of the paths in the domain. Following are all the four cases of the active launch and latch clock edges.

Case 1

If both launch and latch clocks have active high edge, hold relationship is established between the current launch edge and the previous or current latch edge ensuring that the data is not captured by the latch edge coming before the launch edge. Similarly, setup relationship is established between the launch edge and the next latch edge ensuring that the data is captured by the latch edge coming after the launch edge.

...

Inthe following figure, hold and setup relationship is shown between a launch and latch clock with no skew. In case of having different frequencies for launch and latch clock, hold relationship is established between the active launch and latch edges with the minimum difference. Thus, hold relationship gives the minimum delay allowed between launch and latch edges. Whereas, the setup relationship is established between launch and latch edges with minimum difference, hence giving the maximum allowed delay between launch and latch edges.

...

Case 2

If launch and latch clocks have active high and active low edges respectively, in this case hold relationship is established between active high launch edge and the previous active low latch edge with the minimum difference. Similarly, setup relationship is established between launch edge and the next latch edge with the minimum difference.

...

The following figure shows hold and setup relationship between active high launch clock and active low latch clock.

...

Case 3

For the active low launch clock and active high latch clock, the hold relationship gives the minimum delay between active low launch edge and previous active high latch edge. Similarly, setup relationship gives the minimum delay between the active low launch edge and the very next active high latch edge as shown in the following figure.

...

Case 4

If both launch and latch clocks have active low edges, the hold relationship is established between active low launch edge and previous active low latch edge. Similarly, setup relationship is established between the active low launch edge and the very next active low latch edge as shown in the following figure.

...

Slack calculation

In impulse, setup/recovery slack corresponds to the difference between maximum setup/recovery relationship and maximum data arrival time whereas hold/removal slack corresponds to the difference between minimum data arrival and minimum hold/removal relationship.

Setup/Recovery slack = Maximum setup/recovery relationship − Maximum data arrival time
Hold/Removal slack    = Minimum data arrival time − Minimum hold/removal relationship

Anchor
timingreports timingreports

Timing reports

In impulse and nxpython, timing analyzer generates a set of reports presenting respectively the summary of analysis, critical paths of each domain, and violation information. All the timing reports are automatically saved in files (.timing) in ‘logs’ directory after a successful analyzing of the routed design.

STA summary

The file "Summary.timing" contains the report of the timing domains as well as hold/removal and setup/recovery summaries in the design. Such domains are grouped by categories:

...

Maximum Required Relationship

...

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• a summary of the presenting domain (similar to Summary.timing);

• two lists of critical longest paths and shortest paths;

• detailed tables of each found path.

Critical paths table

The critical paths tables show the lists of longest paths and shortest paths for the given timing domain of the design. The details of such critical paths include:

• Slack

• Source (beginning of the path)

• Target (ending of the path)

• Data Delay

• Clock Skew

• Setup/Recovery (longest only)

• Hold/Removal (shortest only)

• Depth

• Note (falling/rising edges of launch and latch clocks)

...

...

Path detail

Following the critical paths table, all the listed critical paths are reported in detail. For each part of the path, the table contents the following information: source (beginning of the path), target (ending of the path), routing delay, internal delay, cumulated delay (from the source of the path), setup/recovery time (for data path), hold/removal time (for data path), clock skew (for data path).

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Revision history

The following table shows the revision history of the Impulse_NXpython specification document: