Table of figures

Hierarchy report providing user modules detection

...

Example of path detail table

Copyright

All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.

Introduction

This document is intended to guide users of NanoXplore Impulse software through all the steps involved in the design flow and the options available in NanoXplore design suite:

...

All commands described in this document for NXpython can be applied to the provided VHDL examples in example folder.

Package description

The provided impulse archive contains the following directories:

• bin       folder contains binary files for each supported Linux distribution

• doc      folder contains documentation files in pdf format

• example folder contains several examples of different projects with design sources in VHDL

• lib64 folder contains dynamic libraries and Python modules for each supported Linux distribution and associated Python version

• share folder contains additional files (vhdl libraries, simulation libraries, etc...)

Installation

To install impulse, the user needs to unpack nxdesignsuite-VERSION.tar.gz file into the installation directory (e.g. /opt/NanoXplore) using the following command:

...

Where servername is the hostname of the server running the license daemon and 27000 is the port the daemon listens to.

Run nxpython

To run nxpython, use the following command:

...

from nxpython import *

Anchor
nxpythonspec nxpythonspec

Nxpython specification

Command list and context

Heraafter a table of all available nxpython commands and the context they affect:

General commands

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the impulse module.

createProject([workingDirectory])

This method is used to create an empty project object. The project can then be loaded or built.

 Arguments:

When no argument is supplied, the working directory will be the one nxpython is launched from.

...

project = createProject("/path/to/working/directory/")

getErrorCount()

This function returns the number of errors issued during Synthesize, Place and Route flow steps.

...

Output:

Errors: 0

getRemarkCount()

This function returns the number of remarks issued during Synthesize, Place and Route flow steps.

...

Output:

Remarks: 10

getWarningCount()

This function returns the number of warnings issued during Synthesize, Place and Route flow steps.

...

Output:

Warnings: 0

listOptions()

This method lists all available options for current project.

...

| Available project options are:
|   +---------------------------------------------------------------------------+
| | Global                                                                                     |
| +-------------------------------+----------+------------------------------+
| |  Autosave                     |      Yes |                       No Yes |
| | +ClearStack                   |       No |                       No Yes |
| |  Dynamic                      |       No |                       No Yes |
| | +InternalReport               |       No |                       No Yes |
| |  MaxRegisterCount             |     2500 |    Value must be an unsigned |
| | +TimingDriven                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 1/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DefaultFSMEncoding           | OneHot   | Binary OneHot OneHotSafe    
                                                            OneHotSafeExtra |
| |  DefaultRAMMapping            |     AUTO |          AUTO RF RAM RAM_ECC |
| |  DefaultROMMapping            |     AUTO |      AUTO LUT RF RAM RAM_ECC |
| |  DisableAssertionChecking     |       No |                       No Yes |
| |  DisableKeepPortOrdering      |       No |                       No Yes |
| |  DisableRAMAlternateForm      |       No |                       No Yes |
| |  DisableROMFullLutRecognition |       No |                       No Yes |
| |  IgnoreRAMFlashClear          |       No |                       No Yes |
| |  ManageUnconnectedOutputs     |    Error |           Error Power Ground |
| |  ManageUnconnectedSignals     |    Error |           Error Power Ground |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 2/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DisableAdderBasicMerge       |       No |                       No Yes |
| |  DisableAdderTreeOptimization |       No |                       No Yes |
| |  DisableAdderTrivialRemoval   |       No |                       No Yes |
| |  DisableDSPAluOperator        |       No |                       No Yes |
| |  DisableDSPFullRecognition    |       No |                       No Yes |
| |  DisableDSPPreOperator        |       No |                       No Yes |
| |  DisableDSPRegisters          |       No |                       No Yes |
| |  DisableLoadAndResetBypass    |       No |                       No Yes |
| |  DisableRAMRegisters          |       No |                       No Yes |
| |  ManageAsynchronousReadPort   |       No |                       No Yes |
| |  ManageUninitializedLoops     |       No |              No Power Ground |
| |  MappingEffort                |     High |              Low Medium High |
| |  OptimizedMux                 |      Yes |                       No Yes |
| | -SynthesizingEffort           |   Medium |              Low Medium High |
| | -UseSynthesisRetiming         |       No |                       No Yes |
| |  VariantAwareSynthesis        |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 1/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  BypassingEffort              |   Medium |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 2/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -SharingEffort                |   Medium |              Low Medium High |
| | -SharingFanout                |      100 |                          100 |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 3/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  CongestionEffort             |     High |              Low Medium High |
| |  DensityEffort                |      Low |              Low Medium High |
| | -PartitioningEffort           |   Medium |              Low Medium High |
| |  RoutingEffort                |   Medium |              Low Medium High |
| | -UnificationEffort            |      Low |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 4/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  PolishingEffort              |     High |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 5/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -DoubleAccess                 |      Yes |                       No Yes |
| | -Permissive                   |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 1/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 2/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 3/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Bitstream                                                               |
| +-------------------------------+----------+------------------------------+
| |  ExhaustiveBitstream          |       No |  No Config Context 
                                                              ConfigContext |
| |  GenerateBitstreamCMIC        |       No |                       No Yes |
| | -MultiBlock                   |       No |                       No Yes |
| |  UnusedPads                   | Floating | Floating WeakPullUp 
                                                               WeakPullDown |
| | -noCfgCtx                     |       No |                       No Yes |
| | -noHeader                     |       No |                       No Yes |
| | -noRun                        |       No |                       No Yes |
| | -noThermalSensor              |       No |                       No Yes |
| | -noWorkaround                 |       No |                       No Yes |
| | -simpleFrames                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+

printError(message)

This function is used to print an error message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by ERROR string so it can be easily found.

When using this method, the global number of errors is incremented by 1.

Arguments:

Example:

printError("It's a trap!")

...

ERROR	|  It's a trap!

printRemark(message)

This function is used to print a remark message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by REMARK string so it can be easily found.

When using this method, the global number of remarks is incremented by 1.

Arguments:

Example:

printRemark("This is a remark")

...

REMARK	|  This is a remark

printText([message])

This function is used to print a message in the impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the impulse output.

Arguments:

Example:

printText('There is no spoon.')

...

| There is no spoon.

printWarning(message)

This function is used to print a warning message in the impulse output. This includes terminal output and log file if set. A warning message is prefixed by WARNING string so it can be easily found.

When using this method, the global number of warnings is incremented by 1.

Arguments:

Example:

printWarning('The cake is a lie.')

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WARNING | The cake is a lie.

setCoreCount(core_count)

This function sets the number of core to use in multi-thread algorithm.

Minimum value is 1. The tool uses the number of logic cores of the computer as a maximum.

Arguments:

Example:

setCoreCount(2)

...

| Setting core count to 2

setDirAutoChange(change_project_dir)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Example:

p = createProject()
setDirAutoChange(False)
p.load('my_path/routed-auto.nym')

setLogDirectory(log_directory)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Example:

setLogDirectory(‘TestLogDirectory’)

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| Setting log directory to TestLogDirectory

usage()

This method displays application usage.

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| Usage:
 |   $> nxpython3
 |     will run nxpython3 in interactive mode
 |     
 |   $> nxpython3 file.py
 |     will run the given python file in nxpython3 in batch mode
 |     
 |   options
 |     several options can be used when running nxpython3.
 |     Options must be placed before the file.py argument.
 |     Any option placed after will be passed to the file.py.
 |       -g or -gui        execute nxpython3 with graphical support
 |       -c or -core CORE  execute nxpython3 with maximum core number
 |       -v or -version    display nxpython3 version
 |       -h or -help       display this help

version()

This method displays application version.

...

| Copyright (C) 2010-2020, NanoXplore, All rights reserved

Expected expressions for NXpython methods

NxPython methods get a standardized format for arguments expecting a path.

This section describes the expression format specific to NX.

Impacted methods:

The following methods allow regular expressions / wildcard formats in order to match with multiple instances:

...

·       getRegisters

·       setSite

·       …

Maintainability:

It is no longer necessary to escape (with the ‘\’ character) special characters for these methods.

...

However, the old format is still compliant and still operates.

User use:

In a usual way, a copy/paste of a path from a log file works for the constraint.

...

Hereafter an example with existing paths and constraints:

Note:

If the user needs to use regular expressions ignoring auto-escaping of special characters, it is possible to set the constraint using back quotes as follow:

addMappingDirective(getModels(“add_`[1-2][0-9]`u_*”), …)

Project related methods

This section presents the methods related to the project object.

addADCLocation(name, location)

This method is used to place an ADC in a specific location

Example:

Example:

project.addADCLocation('WRAPPER_0|ADC_0','ADC1')

addBank(name, dict)

The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.

Arguments:

dict is a dictionary which can take the following keys:

The voltage must be one of the following values:

...

project.addBank('IOB0', {'voltage': '2.5'})

addBanks(dict)

The method addBanks allows user to configure several banks of the FPGA to be used for configuration of inputs/outputs of the HDL module. addBanks use a dictionary as an argument.

Arguments:

Example:

ioBanks = { 'IOB0'  : {'voltage': '2.5'}
                  , 'IOB1'  : {'voltage': '2.5'}
                  , 'IOB2'  : {'voltage': '2.5'}
                  , 'IOB3'  : {'voltage': '2.5'}
                  , 'IOB4'  : {'voltage': '2.5'}
                  , 'IOB5'  : {'voltage': '2.5'}
                  , 'IOB6'  : {'voltage': '2.5'}
                  , 'IOB7'  : {'voltage': '2.5'}
                  , 'IOB8'  : {'voltage': '2.5'}
                  , 'IOB9'  : {'voltage': '2.5'}
                  , 'IOB10' : {'voltage': '2.5'}
                  , 'IOB11' : {'voltage': '2.5'}
                  , 'IOB12' : {'voltage': '2.5'}
          }
project.addBanks(ioBanks)

addBlackBox(name, type, mapping, interface)

The method addBlackBox allows users to define customized mapping of certain HDL modules on the specific FPGA blocks and to dispose the interface of the blocks.

Arguments:

The type argument can only be overridden for specific object types. The available types are:

For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

The argument interface argument specifies the interface mapping between the HDL module and nxpython.

...

When setting ROM value for type argument, the nxpython interface is:

When setting RAM value for type argument, the nxpython interface depends on the mode RAM is being used in:

• RAM mode: Simple port

• RAM mode: Split read/write port (1 port for read and 1 port for write)

• RAM mode: True dual port (2 ports for read/write)

First port:

Second port:

Example:

If the HDL design contains a micro code ROM define in VHDL as:

...

project.addBlackBox('myMicroCode', 'ROM', 'RF', 'AD(addr),DO(micro),CK(clk)')

addBlackBox() : for Preplaced IP

The idea is to offer the possibility to the user to reuse the result of an impulse flow as an IP in a top design.

...

The user can then reuse the result of this first flow in another design. named top, which instanciates the IP entity several times.

...

To specify that an entity of the design top must be taken into account as a preplaced IP, the user has to add the following constraint before the synthesis

...

Among the instances of the ring, some are not supported yet :
PLL, WFG, CR5, SOC_IF, HSSL

...

addDACLocation(

...

name, location)

This method is used to specify the false path for the place a DAC in a specific location

Example:

Example:

project.addDACLocation('WRAPPER_0|DAC_0','DAC1')

addFalsePath(from_list, to_list)

This method is used to specify the false path for the timing paths. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),getRegister('UUT2|dout_reg[61]'))

addFile([library], file)

This method is used to add a HDL source file to the project. The file can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Example:

project.addFile('src/simple.vhd')
project.addFile('src/complex.vhd:VHDL_93')
project.addFile('src/simple_verilog.v:VERILOG_95')
or
project.addFile('myLib', 'src/simple.vhd')

addFiles([library], fileList)

This method is used to add several HDL source files to the project. The files can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Example:

project.addFiles(['src/simple.vhd', 'src/test.vhd'])
or
project.addFiles('myLib', ['src/simple.vhd', 'src/test.vhd'])

addHSSLLocation(pattern,location)

This method is used to set the spot in which a HSSL should be set.

Placement of HSSL elements can also be done during instantiation (with location generic in source code).add

Arguments:

Example:

project.addHSSLLocation('i_hssl_esistream|i_HSSL_ONLY|i_NX_HSSL_FULL|ctrl', 'HSSL2')

addMappingDirective(name, type, mapping)

This method is used to add a mapping directive for Synthesis flow step which overrides the default nxpython mapping behavior for a specific HDL module or instance.

Arguments:

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The type argument can only be overridden for specific object types. For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

Example:

If the HDL design named myTest contains a small 3 write ports and 3 read ports FIFO named myFifo, nxpython cannot automatically map it into RF or RAM, but user can add a mapping directive to map it into DFF:

...

addMaxDelayPath(from_list, to_list, delay)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addMaxDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                        getRegister('UUT2|dout_reg[61]'), 3900)

addMemoryInitialization(name, type, file)

This method is used to specify a file that will be used to initialize a specific memory instance.
Arguments:

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The available file formats are:

...

0000
1000
100
10
1

addMinDelayPath(from_list, to_list, delay)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'),
                                     getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1200)

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addmodule addmodule

addModule(model, instance, format)

This method is used to add a HDL module definition to the current project that contains all HDL logic elements including within the model given in argument.

Arguments:

Example:

project = createProject()
project.addModule('mCntrl',      'cntrl',    'cntrl-%')

nxpython reports user modules detection in the hierarchy.rpt (previous figure) file with detailed information including resources used for each module and detailed hierarchy of all modules defined in the current project.

...

addMulticyclePath(from_list, to_list, cycle_count)

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addMulticyclePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                          getRegister('UUT2|dout_reg[61]'), 2)

addObstruction(name, column, row, width, height)

This method is used to create an obstruction object which will be removed from impulse resources for Place & Route steps.

Arguments:

Example:

project = createProject()
project.load('synthesize.nym')
project.addObstruction('obstr', 10, 2, 15, 5)

Anchor
addpad addpad

addPad(name, parameters)

This method allows user to configure an input/output of the HDL module into specific pad of the FPGA. For the given pad, the configuration has two basic argument (name and parameters).

Arguments:

The parameters argument is a dictionary which can take the following keys:

...

The I/O differential (Default False) activation is conditioned depending on standard:

In case of differential mode, the user must only declare the “_P” pad. The associated differential “_N” pad will be automatically set by the software with the same parameters.

...

As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and noise limitation plus power consumption:

The weakTermination key must respect the following values:

...

Min and max values depend on the variant and the bank voltage.

...

The terminationReference key is used only if termination is set (Default '-'). It must respect the following criteria to be set to ‘Floating’ value otherwise it should always be defined as ‘VT’.

Unit of inputSignalSlope key is V/ns in the range [0.5;20] (Default 0).

...

When set to ‘True”, the turbo key (Default False) specifies that the input buffer of the pad is in turbo mode. As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and power consumption:

The registered key (Default '') allows user to merge registers into Input/Output pads. This key can take the following values:

...

#LVDS implementation
project.addPad( 'spw_rxd[0]' : {'location': 'IOB19_D16P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT', 'turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_rxs[0]' : {'location': 'IOB19_D17P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT','turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_txd[0]' : {'location': 'IOB19_D14P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})
project.addPad( 'spw_txs[0]' : {'location': 'IOB19_D15P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})

addPads(pads)

This method is used to configure inputs/outputs of the HDL module into specific pads of the FPGA. The argument is a dictionary that associates the HDL input/output name to a dictionary, which can contain some keys (location, type, weakTermination, slewRate, termination, inputDelayLine, outputDelayLine, differential, terminationReference, turbo) as defined in addPad(name, parameters).

Arguments:

Example:

#LVCMOS implementation
pads = {'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	  'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination':
            'PullUp', 'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 
           'differential': False, 'turbo': True}
          }
project.addPads(pads)

...

addPin(name, location)

This method allow user to configure an input/output of the HDL module into specific pin of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments

Example:

project.addPin('A', 'TUI200')

addPins(pins)

This method allow user to configure inputs/outputs of the HDL module into specific pins of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments:

Example:

pins = {
	  'A': 'TUI200',
	 'B': 'TUI201'
          }
project.addPins(pins)

Anchor
addparam addparam

addParameter(name, value)

This method allows user to specify the value of the top design generic parameters.

Arguments:

Example:

project.addParameter('BusWidth', '16')
project.addParameter('Key_size', '2')
NB_PIPE_ROW_WG1 = 5 
NB_PIPE_ROW_WG2 = 7 
NB_PIPE_ROW_WG3 = 3 
#parameter list for VHDL design
project.addParameter('NB_PIPE_ROW_WG1', str(NB_PIPE_ROW_WG1))
project.addParameter('NB_PIPE_ROW_WG2', str(NB_PIPE_ROW_WG2))
project.addParameter('NB_PIPE_ROW_WG3', str(NB_PIPE_ROW_WG3))

Anchor
addparameters addparameters

addParameters(parameters)

In case of a large number of parameters, a parameter dictionary can be created consisting of the name of the parameter as a key and its respective value. Both name and value must be string.

Arguments:

Example:

parameters = {'BusWidth': '16', 'Key_size': '2', ...}
project.addParameters(parameters)

addPLLLocation(pattern, location)

This method is used to set the spot in which a PLL should be set.

Placement of PLL elements can also be done during instantiation (with location generic in source code).

Arguments:

Example:

#placing pll0, pll1, pll2, pll3 in different CKGs
project.addPLLLocation('pll0', 'CKG1.PLL1')
project.addPLLLocation('pll1', 'CKG2.PLL1')
project.addPLLLocation('pll2', 'CKG3.PLL1')
project.addPLLLocation('pll3', 'CKG4.PLL1')
#placing a PLL located in a sub-hierarchy of the design
project.addPLLLocation('FIR_MF|CLKG|PLL_20_160', 'CKG4.PLL1')

Anchor
addregion addregion

addRegion(name, column, row, width, height, exclusive)

This method is used to create a region among the FPGA resources where HDL elements will be placed during Place step.

Arguments:

Example:

project = createProject()
p.addRegion('ALU',      13, 6, 14, 6)
p.addRegion('REGISTER', 22, 6, 23, 6, True)

addRingLocation(name, location)

This method is used to place an instance in the I/O ring of the FPGA. addRingLocation can be used instead of addPLLLocation, addWFGLocation or addPin.

Example:

Example:

project.addRingLocation('PLL0','CKG1.PLL1')
project.addRingLocation('WFG_3','CKG4.WFG_C1')

addRingLocations(dictionary)

In case of a large number of instances to be placed in the I/O Ring, a dictionary can be created consisting in the name of the instance as a key and its association location. Both name and location must be string.

Arguments:

Example:

rings = { 'PLL0' : 'CKG1.PLL1', 
               'PLL1' : 'CKG2.PLL1',
               'WFG_0' : 'CKG1.WFG_C1',
               'WFG_1' : 'CKG2.WFG_C1' }
project.addRingLocations(rings)

addVerilogIncludeDirectory(directory)

This method is used to add an extra directory containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Example:

project.addVerilogIncludeDirectory('include’)
or
project.addVerilogIncludeDirectory('../lib’)

addVerilogIncludeDirectories(directoryList)

This method is used to add several extra directories containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Example:

project.addVerilogIncludeDirectories(['include’, ‘../lib’])

addVlogDefine(name,value)

This method is used to add a parameter definition for Verilog files.

Arguments:

Example:

project.addVlogDefine('G_DATA_SIZE’,'8')

addVlogDefines(dictionnary)

This method is used to add parameters definition for Verilog files.

Arguments:

Example:

project.addVlogDefines({'G_DATA_SIZE’:'8','G_ADDR_SIZE’:'16'})

addWFGLocation(name, location)

This method is used to set the spot in which a WFG should be set.

Placement of WFG elements can also be done during instantiation (with location generic in source code).

Arguments:

Valid locations depend on the variant:

Example:

project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)

...

importSdcFile(filePath)

This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.

Arguments:

Example:

project.applySdcFileimportSdcFile(./sdc_directory/constraints.sdc)

clearBanks()

clearBanks() method remove all bank specification previously added in the project.

...

project = createProject()
project.addBank('IOB0', {'voltage': '2.5'})
project.clearBanks()

clearFabricPrePlaceConstraints(regionName)

Clears all preplacing constraints for fabric elements. It removes the impact of the setSite constraint:

...

If no argument is set, constraints for the whole fabric are cleared.

Arguments:

Example:

project = createProject()
project.setSite('i_cpt_0|s_cpt_out_reg[0]', 'TILE[3x2]')
project.clearFabricPreplacedConstraints()
project.setSite('i_cpt_0|s_cpt_out_reg[0]', 'TILE[4x2]')

clearPLLs()

clearPLLs() method remove specification and location for PLLs previously added in the project.

...

project = createProject()
project.addPLLLocation('pll_0', 'CKG2.PLL1')
project.clearPLLs()

clearPads()

clearPads() method remove all inputs/outputs of the HDL module previously configured into specific pads of the FPGA.

...

project = createProject()
pads = {
	'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination': 'PullUp', 
          'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 'differential': False, 
         'turbo': True}
project.addPads(pads))
project.clearPads()

clearPins()

clearPins() method remove all inputs/outputs of the HDL module previously configured into specific pins of the embedded FPGA

...

project = createProject()
pins = {
	'A': 'TUI200',
	'B': 'TUI201'
          }
project.addPins(pins)
project.clearPins()

clearWFGs()

clearWFGs() method remove specification and location for WFGs previously added in the project.

...

project = createProject()
project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)
project.clearWFGs()

Anchor
confinemodule confinemodule

confineModule(name, region)

This method allows to confine a module into a user defined region of the FPGA.

Arguments:

When a module is added to the current project with command, nxpython will generate a module name with automatic incremental syntax in case of listing different modules with similar names. 

...

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a HDL module into a specific region. The aim of constrainModule is to provide a unique and simple function to perform the whole region driven flow described in Creating and handling regions section.

...

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

Arguments:

Example:

#hierarchy argument is extracted from hierarchy.rpt     
# hierarchy, module name, type, col, row, width, height, regionname, exclusive
project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3,     'TIMER',    False)

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a virtual module into a specific region. The aim of this function is to identify source and destination registers in order for all logic elements (LUT, carry) between these registers to be placed into a region created with the regionName argument.

...

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

Arguments:

Example:

 #sourceList, targetList, module name, type, col, row, width, height, region name, exclusive
project.constrainPath(['cntrl|state_reg*'], ['cntrl|state_reg*', 'cntrl|*Write_reg'], 'TEST', 6, 2, 1, 1, 'TEST', True)

createAnalyzer

If a targeted design is already routed, user can launch static timing analysis by creating a timing analyzer.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createAnalyzer()

createClock(target, name, period, [rising, falling])

This method is used to create a clock constraint of a timing point. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

...