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General

destroy()

This method is used to destroy the analyzer object.

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analyzer = project.createAnalyzer()
analyzer.launch()
analyzer.destroy()

preAnalyze()

This method is used to pre-analyze and check if each timing constraint is valid or not.

This method takes no argument.

Example:

analyzer = project.createAnalyzer()
analyzer.createClock(target=getPort('clk'),name='clk', period=10.0)
analyzer.preAnalyze()

launch(parameters)

This method is used to run the static timing analysis.

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preAnalyze()

This method is used to analyze timing constraints without running the static timing analysis.

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project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
analyzer = project.createAnalyzer()
analyzer.preAnalyze()

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project. This constraint is used by timing driven algorithms and static timing analysis.

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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
project.developCKGs()
project.createGeneratedClock(source = 'getWFGOutput(wfg_clk[1])', target= 'getRegister(data_reg[0])', name='clk1_div2', divideBy = 2)

setAnalysisConditions(conditions = 'conditions')

This method is used to specify the chip conditions for the static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.

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project.setAnalysisConditions(conditions = 'worstcase')

setCaseAnalysis(value = 'value', netList = netList)

This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.

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project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(value = '1', netList = getNet(sel))

clearTimingConstraints()

This method is used to clear all design constraints from the current project.
Cleared constraints can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

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p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.clearTimingConstraints()

Clock Creation

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. By default, the unit defined is in ns.

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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5)

createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)

This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.

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The diagram of the above command would be:

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Clock Relationship

setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)

This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis. 

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project = createProject()
project.load('routed.nym')
project.createClock(name ='clk1', period = 2.7, target= 'getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])')
project.createClock(name = 'clk2', period = 5, rising = 0, falling = 2, target= 'getClockNet(CLOCK[2])')    
project.setClockGroup(group1 = 'getClock(clk1)', group2 = 'getClock(clk2)', option = 'exclusive')

Delay Path

setMaxDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

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project = createProject()
project.load('routed.nym')
project.setMaxDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', delay = 3.9)
project.setMaxDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)         
project.setMaxDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 4.0) 
project.setMaxDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)  
project.setMaxDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

setMinDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

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project = createProject()
project.load('routed.nym')
project.setMinDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', target = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', delay = 1.2)
project.setMinDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')

This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.

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setFalsePath(source = ‘source', target = 'target’)

This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.

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IO Delay

setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.

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project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name = 'clock',period = 8)
project.setInputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)')

setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This command specifies the data required times at the specified output ports relative to the clock. The clock must refer to a clock defined in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings could be in ns or ps.

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project = createProject()
project.load('routed.nym')
project.createClock(target = getClockNet('CLK'), name = 'CLK', period = 8)
project.setOutputDelay(clock = 'getClock('CLK'), clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)')

Report Request

removeTimingConstraint(id)

This method is used to remove a timingconstraint from the current project.
Remove constraint can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

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p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.removeDesignConstraint(1)
p.createClock(target=getClockNet('clk1'),name='clk1',period=40.000,rising=0,falling=20.000) #Clk1 is now with 25 MHz frequency

addReportTimingRequest(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path.

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Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportTimingRequest(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch()

reportTiming(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path.

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Timing_analysis = p.createAnalyzer()
Timing_analysis.ReportTimingPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')

addReportPathRequest(source = ‘source_pin', target = 'target_pin’)

This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

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reportPath(source = ‘source_pin', target = 'target_pin’)

This method gives the shortest and the longest delays of a path.

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removeReportTimingRequest(id)

This method is used to remove a reportTiming from the current project.

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Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportTimingRequest(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.removeReportRequest(1)
Timing_analysis.addReportTimingRequest(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[3])')
Timing_analysis.launch()

removeReportRequest(id)

This method is used to remove a reportPath from the current project.

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