Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

VCO

Out

std_logic

VCO output : Fvco = fbk_intdiv * 2**(fbk_div_on - ref_div_on + 1) * clk_ref_freq

Connectivity: WFG inputs

D1…D3

Out

std_logic

Divided clocks. Fvco frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128

Important note: D1, D2 and D3 outputs are reset while PLL RDY is not asserted.

Connectivity: WFG inputs

OSC

Out

std_logic

Internal 200 MHz oscilator

Connectivity :WFG inputs, delay calibration system

RDY

Out

std_logic

High when PLL is locked

Connectivity: RDY inputs of WFGs, fabric…

Ports

Direction

Type

Description

REF

In

std_logic

Reference clock input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled.

FBK

In

std_logic

External FeedBack input

Connectivity: semi-dedicated clock inputs, clock trees (low skew network)

R

In

std_logic

Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL

VCO

Out

std_logic

VCO output:

- Internal feedback: Fvco = 2 * (fbk_intdiv + 2) * clk_ref_freq / (ref_intdiv + 1)

- External feedback: Fvco = (pattern_end + 1) / n_sim_pat * clk_ref_freq / (ref_intdiv + 1)

Where n_sim_pat is the number of similar patterns sequence found in pattern_end+1 MSB bits of pattern.

REFO

Out

std_logic

Output of the REFerence divider. The division factor is set by the generic “ref_intdiv”

LDFO

Out

std_logic

Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv”

DIVP1

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp1”

DIVP2

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp2”

DIVP3

Out

std_logic

This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp3o2”

DIVO1

Out

std_logic

This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divouto1”

DIVO2

Out

std_logic

This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divoutp3o2”

OSC

Out

std_logic

200 MHz coming from 400MHz internal oscilator

Connectivity :WFG inputs, delay calibration engine

PLL_LOCKED

Out

std_logic

High when PLL is locked

Connectivity: RDY inputs of WFGs, fabric…

CAL_LOCKED

Out

std_logic

High when the automatic calibration procedure of the current FPGA quarte area is complete

Connectivity: fabric