Table of

...

Figures

Hierarchy report providing user modules detection

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Example of path detail table

Copyright Notice

All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.

Introduction

This document is intended to guide users of NanoXplore NXmap Impulse software through all the steps involved in the design flow and the options available in NanoXplore design suite:

• nxmap impulse is a graphical interface that allows user to view and compile an existing project.

• nxpython is a wrapper around Python executable that allows user to control nxmap impulse software as a wrapper. It fully supports Python syntax, structures and external modules.

• The creation of a new project can be performed with both nxmap impulse and nxpython tools.

All commands described in this document for NXpython can be applied to the provided VHDL examples in example folder.

Package

...

Description

The provided nXmap impulse archive contains the following directories:

• bin       folder contains binary files for each supported Linux distribution

• doc      folder contains documentation files in pdf format

• example folder contains several examples of different projects with design sources in VHDL

• lib64 folder contains dynamic libraries and Python modules for each supported Linux distribution and associated Python version

• share folder contains additional files (vhdl libraries, simulation libraries, etc...)

Installation

To install nxmapimpulse, the user needs to unpack nxmapnxdesignsuite-VERSION.tar.gz file into the installation directory (e.g. /opt/NanoXplore) using the following command:

$> tar xzf nxmapnxdesignsuite-VERSION.tar.gz -C /opt/NanoXplore

...

Where servername is the hostname of the server running the license daemon and 27000 is the port the daemon listens to.

Run

...

NXPython

To run nxpython, use the following command:

$> /opt/NanoXplore/NXmap3impulse/VERSION/bin/nxpython

To use the nanoxmap module in python, user must first call the following command in nxpython:

from nxmapnxpython import *

Anchor
nxpythonspec nxpythonspec

...

NXPython Specification

Command

...

List and

...

Context

Heraafter a The table of below list all available nxpython commands and the context they affect:

General commands

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the nxmap impulse module.

createProject([workingDirectory])

This method is used to create an empty project object. The project can then be loaded or built.

...

project = createProject("/path/to/working/directory/")

getErrorCount()

This function returns the number of errors issued during Synthesize, Place and Route flow steps.

...

Output:

Errors: 0

getRemarkCount()

This function returns the number of remarks issued during Synthesize, Place and Route flow steps.

...

Output:

Remarks: 10

getWarningCount()

This function returns the number of warnings issued during Synthesize, Place and Route flow steps.

...

Output:

Warnings: 0

listOptions()

This method lists all available options for current project.

...

| Available project options are:
|   +---------------------------------------------------------------------------+
| | Global                                                                                     |
| +-------------------------------+----------+------------------------------+
| |  Autosave                     |      Yes |                       No Yes |
| | +ClearStack                   |       No |                       No Yes |
| |  Dynamic                      |       No |                       No Yes |
| | +InternalReport               |       No |                       No Yes |
| |  MaxRegisterCount             |     2500 |    Value must be an unsigned |
| | +TimingDriven                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 1/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DefaultFSMEncoding           | OneHot   | Binary OneHot OneHotSafe    
                                                            OneHotSafeExtra |
| |  DefaultRAMMapping            |     AUTO |          AUTO RF RAM RAM_ECC |
| |  DefaultROMMapping            |     AUTO |      AUTO LUT RF RAM RAM_ECC |
| |  DisableAssertionChecking     |       No |                       No Yes |
| |  DisableKeepPortOrdering      |       No |                       No Yes |
| |  DisableRAMAlternateForm      |       No |                       No Yes |
| |  DisableROMFullLutRecognition |       No |                       No Yes |
| |  IgnoreRAMFlashClear          |       No |                       No Yes |
| |  ManageUnconnectedOutputs     |    Error |           Error Power Ground |
| |  ManageUnconnectedSignals     |    Error |           Error Power Ground |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 2/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DisableAdderBasicMerge       |       No |                       No Yes |
| |  DisableAdderTreeOptimization |       No |                       No Yes |
| |  DisableAdderTrivialRemoval   |       No |                       No Yes |
| |  DisableDSPAluOperator        |       No |                       No Yes |
| |  DisableDSPFullRecognition    |       No |                       No Yes |
| |  DisableDSPPreOperator        |       No |                       No Yes |
| |  DisableDSPRegisters          |       No |                       No Yes |
| |  DisableLoadAndResetBypass    |       No |                       No Yes |
| |  DisableRAMRegisters          |       No |                       No Yes |
| |  ManageAsynchronousReadPort   |       No |                       No Yes |
| |  ManageUninitializedLoops     |       No |              No Power Ground |
| |  MappingEffort                |     High |              Low Medium High |
| |  OptimizedMux                 |      Yes |                       No Yes |
| | -SynthesizingEffort           |   Medium |              Low Medium High |
| | -UseSynthesisRetiming         |       No |                       No Yes |
| |  VariantAwareSynthesis        |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 1/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  BypassingEffort              |   Medium |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 2/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -SharingEffort                |   Medium |              Low Medium High |
| | -SharingFanout                |      100 |                          100 |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 3/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  CongestionEffort             |     High |              Low Medium High |
| |  DensityEffort                |      Low |              Low Medium High |
| | -PartitioningEffort           |   Medium |              Low Medium High |
| |  RoutingEffort                |   Medium |              Low Medium High |
| | -UnificationEffort            |      Low |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 4/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  PolishingEffort              |     High |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 5/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -DoubleAccess                 |      Yes |                       No Yes |
| | -Permissive                   |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 1/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 2/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 3/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Bitstream                                                               |
| +-------------------------------+----------+------------------------------+
| |  ExhaustiveBitstream          |       No |  No Config Context 
                                                              ConfigContext |
| |  GenerateBitstreamCMIC        |       No |                       No Yes |
| | -MultiBlock                   |       No |                       No Yes |
| |  UnusedPads                   | Floating | Floating WeakPullUp 
                                                               WeakPullDown |
| | -noCfgCtx                     |       No |                       No Yes |
| | -noHeader                     |       No |                       No Yes |
| | -noRun                        |       No |                       No Yes |
| | -noThermalSensor              |       No |                       No Yes |
| | -noWorkaround                 |       No |                       No Yes |
| | -simpleFrames                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+

printError(message)

This function is used to print an error message in the nxmap impulse output. This includes terminal output and log file if set. An error message is prefixed by ERROR string so it can be easily found.

...

ERROR	|  It's a trap!

printRemark(message)

This function is used to print a remark message in the nxmap impulse output. This includes terminal output and log file if set. An error message is prefixed by REMARK string so it can be easily found.

...

REMARK	|  This is a remark

printText([message])

This function is used to print a message in the nxmap impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the nxmap impulse output.

Arguments:

...

| There is no spoon.

printWarning(message)

This function is used to print a warning message in the nxmap impulse output. This includes terminal output and log file if set. A warning message is prefixed by WARNING string so it can be easily found.

...

WARNING | The cake is a lie.

setCoreCount(core_count)

This function sets the number of core to use in multi-thread algorithm.

...

| Setting core count to 2

setDirAutoChange(change_project_dir)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

...

p = createProject()
setDirAutoChange(False)
p.load('my_path/routed-auto.nym')

setLogDirectory(log_directory)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

...

| Setting log directory to TestLogDirectory

usage()

This method displays application usage.

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| Usage:
 |   $> nxpython3
 |     will run nxpython3 in interactive mode
 |     
 |   $> nxpython3 file.py
 |     will run the given python file in nxpython3 in batch mode
 |     
 |   options
 |     several options can be used when running nxpython3.
 |     Options must be placed before the file.py argument.
 |     Any option placed after will be passed to the file.py.
 |       -g or -gui        execute nxpython3 with graphical support
 |       -c or -core CORE  execute nxpython3 with maximum core number
 |       -v or -version    display nxpython3 version
 |       -h or -help       display this help

version()

This method displays application version.

...

| Copyright (C) 2010-2020, NanoXplore, All rights reserved

Expected expressions for NXpython methods

NxPython methods get a standardized format for arguments expecting a path.

This section describes the expression format specific to NX.

Impacted methods:

The following methods allow regular expressions / wildcard formats in order to match with multiple instances:

...

·       getRegisters

·       setSite

·       …

Maintainability:

It is no longer necessary to escape (with the ‘\’ character) special characters for these methods.

...

However, the old format is still compliant and still operates.

User use:

In a usual way, a copy/paste of a path from a log file works for the constraint.

...

addMappingDirective(getModels(“add_`[1-2][0-9]`u_*”), …)

Project related methods

This section presents the methods related to the project object.

addBank(name, dict)

The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.

...

project.addBank('IOB0', {'voltage': '2.5'})

addBanks(dict)

The method addBanks allows user to configure several banks of the FPGA to be used for configuration of inputs/outputs of the HDL module. addBanks use a dictionary as an argument.

...

ioBanks = { 'IOB0'  : {'voltage': '2.5'}
                  , 'IOB1'  : {'voltage': '2.5'}
                  , 'IOB2'  : {'voltage': '2.5'}
                  , 'IOB3'  : {'voltage': '2.5'}
                  , 'IOB4'  : {'voltage': '2.5'}
                  , 'IOB5'  : {'voltage': '2.5'}
                  , 'IOB6'  : {'voltage': '2.5'}
                  , 'IOB7'  : {'voltage': '2.5'}
                  , 'IOB8'  : {'voltage': '2.5'}
                  , 'IOB9'  : {'voltage': '2.5'}
                  , 'IOB10' : {'voltage': '2.5'}
                  , 'IOB11' : {'voltage': '2.5'}
                  , 'IOB12' : {'voltage': '2.5'}
          }
project.addBanks(ioBanks)

addBlackBox(name, type, mapping, interface)

The method addBlackBox allows users to define customized mapping of certain HDL modules on the specific FPGA blocks and to dispose the interface of the blocks.

...

project.addBlackBox('myMicroCode', 'ROM', 'RF', 'AD(addr),DO(micro),CK(clk)')

addBlackBox() : for Preplaced IP

The idea is to offer the possibility to the user to reuse the result of an nxmap impulse flow as an IP in a top design.

...

The user can then reuse the result of this first flow in another design. named top, which instanciates the IP entity several times.

Nxmap Impulse will use the result of synthesis and place from the first flow and replicate then in the top flow

...

Among the instances of the ring, some are not supported yet :
PLL, WFG, CR5, SOC_IF, HSSL

addDSPLocation(pattern, place)

This method is used to select the spot in which a DSP should be placed before launching Place step execution.

...

addFalsePath(from_list, to_list)

This method is used to specify the false path for the timing paths. This constraint is used by timing driver algorithms and static timing analysis.

...

addFile([library], file)

This method is used to add a HDL source file to the project. The file can be added to a specific library by passing its name as the first optional library argument. The default library is work.

...

project.addFile('src/simple.vhd')
project.addFile('src/complex.vhd:VHDL_93')
project.addFile('src/simple_verilog.v:VERILOG_95')
or
project.addFile('myLib', 'src/simple.vhd')

addFiles([library], fileList)

This method is used to add several HDL source files to the project. The files can be added to a specific library by passing its name as the first optional library argument. The default library is work.

...

addHSSLLocation(pattern,location)

This method is used to set the spot in which a HSSL should be set.

Placement of HSSL elements can also be done during instantiation (with location generic in source code).add

Arguments:

...

project.addHSSLLocation('i_hssl_esistream|i_HSSL_ONLY|i_NX_HSSL_FULL|ctrl', 'HSSL2')

addMappingDirective(name, type, mapping)

This method is used to add a mapping directive for Synthesis flow step which overrides the default nxpython mapping behavior for a specific HDL module or instance.

...

addMaxDelayPath(from_list, to_list, delay)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Example:

project = createProject()
project.load('routed.nym')
project.addMaxDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                        getRegister('UUT2|dout_reg[61]'), 3900)

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The available file formats are:

...

Type

addMemoryInitialization(name, type, file)

This method is used to specify a file that will be used to initialize a specific memory instance.
Arguments:

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The available file formats are:

...

0000
1000
100
10
1

addMinDelayPath(from_list, to_list, delay)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

...

project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'),
                                     getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1200)

Anchor
addmodule addmodule

addModule(model, instance, format)

This method is used to add a HDL module definition to the current project that contains all HDL logic elements including within the model given in argument.

...

hierarchy.rpt also allows to check if pattern expression provided for model and instance arguments have been fully accepted by nxpython tool. User must especially be careful about the regular expression operator '*', which is accepted whereas the can use the wildcard operator '*' is not supported. See full details with an incorrect example.

Example:

project = createProject()
project.addModule('mAlu*',         'alu',        'alu-%')
#incorrect pattern
project.addModule('mCntrl',        'cntrl',      'cntrl-%')
project.addModule('mRegister*', 'register', 'cntrl-%') #incorrect pattern

...

Example:

project = createProject()
project.addModule('mAlu*',         'alu',        'alu-%') #correct pattern
project.addModule('mCntrl',        'cntrl',      'cntrl-%')
project.addModule('mRegister*', 'register', 'cntrl-%') #correct pattern

addMulticyclePath(from_list, to_list, cycle_count)

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

...

Name

...

Type

...

Description

...

from_list

addMulticyclePath(from_list, to_list, cycle_count)

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

...

Anchor
addpad addpad

addPad(name, parameters)

This method allows user to configure an input/output of the HDL module into specific pad of the FPGA. For the given pad, the configuration has two basic argument (name and parameters).

...

• LVCMOS (Default)

• LVDS

• LVDS_STR

• SSTL

• HSTL

...

The I/O differential (Default False) activation is conditioned only by the LVDS depending on standard:

In case of differential mode, the user must only declare the “_P” pad. The associated differential “_N” pad will be automatically set by the software with the same parameters.

...

• 2mA (only allowed for LVCMOS standard - Default for LVCMOS standard)

• 4mA (only allowed for LVCMOS standard)

• 8mA

• 16mA

• I (only allowed for SSTL and HSTL standard - LVCMOS standard)

• 12mA (only allowed for LVCMOS standard)

• 16mA (only allowed for LVCMOS standard)

• I (only allowed for SSTL and HSTL standard - Default for SSTL and HSTL standard)

• II (only allowed for SSTL and HSTL standard)

• Undefined (only allowed for LVDS standard - Default for LVDS standard)

As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and noise limitation plus power consumption:

...

• None

• PullDown

• PullUp (Default)

• Keeper

...

The termination key specifies the output impedance of the pad in Ohms. In differential mode, the impedance is two times the value. It’s specified in Ohms, in the range 30 to 80 Ohms (Default is set to minimum value).

Min and max values depend on the variant and the bank voltage.

...

When a key is not in the dictionary, its value is set to default, i.e. 0 for inputDelayLine/outputDelayLine/signalSlope/outputCapacity and False for all the boolean arguments.

...

#LVDS implementation
project.addPad( 'spw_rxd[0]' : {'location': 'IOB19_D16P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT', 'turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_rxs[0]' : {'location': 'IOB19_D17P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT','turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_txd[0]' : {'location': 'IOB19_D14P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})
project.addPad( 'spw_txs[0]' : {'location': 'IOB19_D15P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})

addPads(pads)

This method is used to configure inputs/outputs of the HDL module into specific pads of the FPGA. The argument is a dictionary that associates the HDL input/output name to a dictionary, which can contain some keys (location, type, weakTermination, slewRate, termination, inputDelayLine, outputDelayLine, differential, terminationReference, turbo) as defined in addPad(name, parameters).

...

addPin(name, location)

This method allow user to configure an input/output of the HDL module into specific pin of the embedded FPGA. This method is reserved to embedded variants of FPGA.

...

project.addPin('A', 'TUI200')

addPins(pins)

This method allow user to configure inputs/outputs of the HDL module into specific pins of the embedded FPGA. This method is reserved to embedded variants of FPGA.

...

pins = {
	  'A': 'TUI200',
	 'B': 'TUI201'
          }
project.addPins(pins)

Anchor
addparam addparam

addParameter(name, value)

This method allows user to specify the value of the top design generic parameters.

...

Anchor
addparameters addparameters

addParameters(parameters)

In case of a large number of parameters, a parameter dictionary can be created consisting of the name of the parameter as a key and its respective value. Both name and value must be string.

...

addPLLLocation(pattern, location)

This method is used to set the spot in which a PLL should be set.

...

#placing pll0, pll1, pll2, pll3 in different CKGs
project.addPLLLocation('pll0', 'CKG1.PLL1')
project.addPLLLocation('pll1', 'CKG2.PLL1')
project.addPLLLocation('pll2', 'CKG3.PLL1')
project.addPLLLocation('pll3', 'CKG4.PLL1')
#placing a PLL located in a sub-hierarchy of the design
project.addPLLLocation('FIR_MF|CLKG|PLL_20_160', 'CKG4.PLL1')

addRAMLocation(pattern, place)

This method is used to select the spot in which a RAM should be placed. This method must be used and declared before launching Place step execution.

...

addRingLocation(name, location)

This method is used to place an instance in the I/O ring of the FPGA. addRingLocation can be used instead of addPLLLocation, addWFGLocation or addPin.

...

project.addRingLocation('PLL0','CKG1.PLL1')
project.addRingLocation('WFG_3','CKG4.WFG_C1')

addRingLocations(dictionary)

In case of a large number of instances to be placed in the I/O Ring, a dictionary can be created consisting in the name of the instance as a key and its association location. Both name and location must be string.

...

rings = { 'PLL0' : 'CKG1.PLL1', 
               'PLL1' : 'CKG2.PLL1',
               'WFG_0' : 'CKG1.WFG_C1',
               'WFG_1' : 'CKG2.WFG_C1' }
project.addRingLocations(rings)

addVerilogIncludeDirectory(directory)

This method is used to add an extra directory containing Verilog files to the project. This is used when the included files are external to the working directory.

...

project.addVerilogIncludeDirectory('include’)
or
project.addVerilogIncludeDirectory('../lib’)

addVerilogIncludeDirectories(directoryList)

This method is used to add several extra directories containing Verilog files to the project. This is used when the included files are external to the working directory.

...

project.addVerilogIncludeDirectories(['include’, ‘../lib’])

addVlogDefine(name,value)

This method is used to add a parameter definition for Verilog files.

...

project.addVlogDefine('G_DATA_SIZE’,'8')

addVlogDefines(dictionnary)

This method is used to add parameters definition for Verilog files.

...

project.addVlogDefines({'G_DATA_SIZE’:'8','G_ADDR_SIZE’:'16'})

addWFGLocation(name, location)

This method is used to set the spot in which a WFG should be set.

...

project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)

adjustAperture(regionName, above, left, right, below)

This method is used to move the aperture of a region or the whole design.

...

project.setAperture(6,8,14,12)
project.ajustAperture(2,3,2,2)
p.createRegion('region_0',7,8,9,10)
project.ajustAperture('region_0',2,3,2,2)

applySdcFile(filePath)

This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.

...

project.applySdcFile(./sdc_directory/constraints.sdc)

clearBanks()

clearBanks() method remove all bank specification previously added in the project.

...

project = createProject()
project.addBank('IOB0', {'voltage': '2.5'})
project.clearBanks()

...

clearFabricPrePlaceConstraints(regionName)

Clears all preplacing constraints for fabric elements. It removes the impact of the following constraints:

• setSite

• addRAMLocation

• addDSPLocation

It gives the ability to clear all Fabric elements constraints and add new ones.

If no argument is set, constraints for the whole fabric are cleared.

Arguments:

Example:

project = createProject()
project.addRAMLocation('module0|RAM', 'CGB[3x2]')
project.clearFabricPreplacedConstraints()
project.addRAMLocation('module0|RAM', 'CGB[4x2]')

clearPLLs()

clearPLLs() method remove specification and location for PLLs previously added in the project.

...

project = createProject()
project.addPLLLocation('pll_0', 'CKG2.PLL1')
project.clearPLLs()

clearPads()

clearPads() method remove all inputs/outputs of the HDL module previously configured into specific pads of the FPGA.

...

project = createProject()
pads = {
	'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination': 'PullUp', 
          'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 'differential': False, 
         'turbo': True}
project.addPads(pads))
project.clearPads()

clearPins()

clearPins() method remove all inputs/outputs of the HDL module previously configured into specific pins of the embedded FPGA

...

project = createProject()
pins = {
	'A': 'TUI200',
	'B': 'TUI201'
          }
project.addPins(pins)
project.clearPins()

clearWFGs()

clearWFGs() method remove specification and location for WFGs previously added in the project.

...

project = createProject()
project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)
project.clearWFGs()

Anchor
confinemodule confinemodule

confineModule(name, region)

This method allows to confine a module into a user defined region of the FPGA.

...

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a HDL module into a specific region. The aim of constrainModule is to provide a unique and simple function to perform the whole region driven flow described in Creating and handling regions section.

...

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a virtual module into a specific region. The aim of this function is to identify source and destination registers in order for all logic elements (LUT, carry) between these registers to be placed into a region created with the regionName argument.

...

createAnalyzer

If a targeted design is already routed, user can launch static timing analysis by creating a timing analyzer.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createAnalyzer()

createClock(target, name, period, [rising, falling])

This method is used to create a clock constraint of a timing point. This constraint is used by timing driver algorithms and static timing analysis.

...

project = createProject()
project.load('routed.nym')
project.createClock(getRegisterClock(reg1'), 'clk', 10000)
or
project.createClock(getPort(Clk'), 'clk', 10000)
or
project.createClock(getClockNet('Clk'), 'clk', 10000, 0, 5000)

createGeneratedClock(source, target, name, relationship)

This method is used to create an internally generated clock constraint at a timing point. This constraint is used by timing driver algorithms and static timing analysis.

...

The relationship generated by above command is:

...

createObstruction(name, column1, row1, column2, row2)

This method is used to create an obstruction object which will be removed from nxmap impulse resources for Place & Route steps.

...

project = createProject()
project.load('synthesize.nym')
project.createObstruction('obstr', 10, 2, 24, 6)

Anchor
createregion createregion

createRegion(name, column1, row1, column2, row2, exclusive)

This method is used to create a region among the FPGA resources where HDL elements will be placed during Place step.

...

project = createProject()
p.createRegion('ALU',      13, 6, 14, 6)
p.createRegion('REGISTER', 22, 6, 23, 6, True)

createSimulator()

This method is used to create a simulator object. A simulator object is used to simulate the project with a specified testbench.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createSimulator()

destroyObstruction(name)

This method is used to destroy a given obstruction object.

...

project = createProject()
project.load('synthesize.nym')
project.createObstruction('obstr', 10, 2, 24, 6)
project.destroyObstruction('obstr')

destroyRegion(name)

This method is used to destroy a given region.

...

project = createProject()
project.createRegion('CNTRL',     4, 6,  5, 6)
project.destroyRegion('CNTRL')

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project.

...

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'),getRegister('data_reg[0]'), 'clk1_div2', {'DivideBy': 2})

destroy()

This method is used to destroy the project.

...

Display after destruction
Traceback (most recent call last):
    File "test.py", line 22, in <module>
        project.display()
nxmapimpulse.error: Invalid Request: Obsolete object

display()

This method is used to open current project in nxmap impulse graphic user interface. It can be called several times from the same Python script.

...

exportAsIPCore(file, options)

This method is used to export the synthesized design to an IPCore. An IPCOre is a HDL description (at NX components level) that can be given as part of new source design to nxmap impulse.

The export is different from the save() method as it is done during the second step of synthesis.

...

...

project = createProject()
project.load('/home/user/example/vhdl/simple/native.nym')
options = { ‘coreName’: ‘IPCore’, ‘encrypt’: ‘All’ }
p.exportAsIPCore(‘IPCore.vhd’, options)
p.synthesize()

exportRegions()

This method is used to export all constrainModule constraints in the console. It can be useful if the user modified the region location or size and want to get new constraints to copy them in the script.

...

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3)
project.exportRegions()

exportSites(projectVariable,fileName)

This method is used to export all setSite constraints in a file. It can be useful in order to keep all TILE locations.

...

project.exportSites('p','site_constraints.py')

Anchor
generatebitstream generatebitstream

generateBitstream(file)

This method is used to save the bitstream configuration file to disk. The extension of the target file must be .nxb

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.generateBitstream('bitstream.nxb')

generateSTANetlist(filePath,condition)

This method is used to generate routed netlist and SDF file.

...

project.route()
project.generateSTANetlist(./output_files/routed_sta_file)

...

setDeviceID

...

(id)

This method is used to change the Device ID in the bitstream header before generating it.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
p.setDeviceID(10) #Set Device ID to 0xA
project.generateBitstream('bitstream.nxb')

...

getAnalyzer()

This method returns the project current directory. This directory is used as root for all relative paths passed as argument of generic functions and/or methods. The default value of the directory is the current working directorycurrent analyzer associated to the project to manage STA.

This method takes no argument.

...

project = createProject()
directorya = project.getDirectorycreateAnalyzer()

...

project.getAnalyzer().launch()

getDirectory()

This method returns the project current directory. This directory is used as root for all relative paths passed as argument of generic functions and/or methods. The default value of the directory is the current working directory.

This method takes no argument.

Example:

project = createProject()
directory = project.getDirectory()

getHierInfo()

This method returns the detailed hierarchy into a dictionary variable.

This method takes no argument.

Example:

project = createProject()
hierarchy = project.getHierInfo()
printText(hierarchy)

getLowskewSignals(ignoreTop, showCandidates)

This method is used to get lowskew signals or potential candidates to be lowskew signals. It gives a table of impacted lobes for each lowskew signal

...

getProject()

This method returns the project object.

...

createProject()
project = getproject()

getTimingUnit()

This method returns the timing unit used in STA.

...

printText(project.getTimingUnit())

getTopCellName()

This method returns the name of the top HDL module. If the HDL module is defined inside a library, the name is prefixed by the name of the library followed by a # character.

...

Output:

myLib#simple

getVariantName()

This method returns the variant of the project. The default value of the variant is 'NG-MEDIUM'.

...

Output:

NG-MEDIUM

initRegister(command, value)

This method is used to write in registers during the generation of bitstream.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.initRegister('SPI_CTRL', '0x01f4003f')
project.generateBitstream('bitstream.nxb')

limitLowskew(signal, lobes)

This method is used to limit a lowskew signal to be used in only specified lobes.

...

project.limitLowskew('clk_right','Rx1,Rx2,Rx3,Rx4')

listAvailableLocations(name)

This method is used to print all available pads for a bank or for all banks of a variant .

...

project.listAvailableLocations()
project.listAvailableLocations('IOB10')

load(file)

This method is used to load a previously saved project from disk. The input format (file extension) must be .nym (nxmap impulse archive).

Arguments:

...

project = createProject('/home/user/example/vhdl/simple')
project.load('synthesized.nym')

...

modifyPad(name,

...

parameters)

This method is used to modify the location or the size configuration of an existed regionpad.

This method takes the same parameters as addPad method.

Parameters that only affect the configuration and not the placing can be changed at any time.

Arguments:

Example:

project.addPad('output[0]',{'location':'IOB10D09P', 'standard': 'LVCMOS', 'drive' :'2mA', 'slewRate':'Slow'})
project.modifyPad('output[0]',{'drive' :'16mA', 'slewRate':'Fast'})

modifyRegion(name, column1, row1, width, height, exclusive)

This method is used to modify the location or the size of an existed region.

Arguments:

Example:

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3)

...

place

...

()

This method is used to run the place algorithm on a project.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.setOption('TimingDriven', 'Yes')
project.place()

...

printHierInfo(

...

)

This method allows to progress through project to a given flow step.

Arguments:

...

Name

...

Type

prints the detailed hierarchy of a project with the module matched and all instances per module.

This methods takes no argument.

Example:

project = createProject()
project.progress('Synthesize', 3)
project.printHierInfo()

progress(step, number)

This method allows to progress through project to a given flow step.

Arguments:

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.progress('Place', 3)

rejectLowskew(signal)

This method avoids local lowskew signal to be converted in global lowskew signal.

...

project.rejctLowskew('sub_module0|local_reset')

removeFile(libName, filePath)

This method allows to remove a file from a project.

...

project.addFile('work','sub_modul_0.vhd')
project.addFile('work','sub_modul_1.vhd')
project.removeFile('work','sub_modul_0.vhd')
project.removeFile(sub_modul_1.vhd')

removeFiles()

This method allows to remove files from a project.

...

project.addFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])
project.removeFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])

removeSoftModules(libName, fileList)

This method allows to remove all HDL soft modules from a project.

...

reportDesignComplexity(html_file)

This method reports the design complexity, clock domain by clock domain, indicating the logic depth for all paths of the design and illustrates it with a chart in HTML format:

Example:

project.reportDesignComplexity('design_complexity.html')

The output HTML file looks like:

...

Anchor
reportinstances reportinstances

reportInstances()

This method reports the instances utilization of the programmed design on the current variant. Three tables are printed. The first one contains values for all types of instances. The instances are grouped by categories:

...

Output:

...

reportLowskewSignals(logfile)

This method reports the lowskew signals:

Example:

project.reportLowskewSignals('lowskew_report')

Anchor
reportports reportports

reportPorts()

This method reports the ports found in HDL source and the ones manually added by user in the project. The report displays the following information:

...

project = createProject()
project.load('/home/user/example/vhdl/simple/placed.nym')
project.reportPorts()

Anchor
reportregions reportregions

reportRegions()

This method reports occupied resources by HDL elements within every region created in the FPGA.

...

The report displays the amount and percentage placed in the created region:

...

resetTimingConstraints()

This method is used to reset all timing constraints for current project.

...

project = createProject()
project.load('/home/user/simple/routed.nym')
project.resetTimingConstraints()

Anchor
route route

route()

This method is used to run the route algorithm on a project.

...

project = createProject()
project.load('/home/user/example/vhdl/simple/placed.nym')
project.setOption('TimingDriven', 'Yes')
project.route()

Anchor
savefile savefile

save(file,conditions)

This method is used to save the current project into a nxmap impulse archive (.nym), a design netlist (.v or .vhd) or to generate a sdf file containing delays of the design supporting bestcase, worstcase and typical scenarios.

...

project = createProject()
project.load('native.nym')
project.synthesize()
project.save('synthesized.nym')
project.save('synthesized.vhd')
project.route()
project.save(‘routed.vhd’)
project.save('sdf_file_bestcase.sdf','bestcase') #generate a sdf file defining bestcase scenario
project.save('sdf_file_worstcase.sdf','worstcase') #generate a sdf file defining worstcase scenario
project.save('sdf_file_typical.sdf','typical') #generate a sdf file defining typical scenario
project.save(‘routed.sdf’)

setAnalysisConditions(conditions)

This method is used to specify the chip conditions for static timing analysis.

...

project.setAnalysisConditions(WorstCase)

Anchor
setaperture setaperture

setAperture(column1, row1, column2, row2)

This method is used to define the size of aperture. The default size value is bounded to the Fabric dimensions.

...

project = createProject()
project.load('synthesize.nym')
project.setAperture(10, 2, 24, 6)

setCaseAnalysis(value, net_list)

This method is used to specify a constant logic value to the given tests.

...

setClockGroup(group1_list, group2_list, option)

This method is used to specify which clocks are not related. This constraint is used by timing driver algorithms and static timing analysis. 

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet(CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet(CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'),getClock('clk2'), 'exclusive')

setDescription(description)

This method is used to set a description to a project.

...

project = createProject()
project.setDescription('NXmapImpulse project for training')

setDirectory(directory)

This method is used to change project directory.

...

project = createProject()
project.setDirectory('./new_dir')

Anchor
setfocus setfocus

setFocus(column, row)

This method is used to specify the position of the focus.

...

project = createProject()
project.load('synthesize.nym')
project.setFocus(4, 4)

setGCKCount(count)

This method is used to limit the number of GCK at the end of Placing step 2.

...

project.setGCKCount(20)

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500,getPort('RST'))

Anchor
setoption setoption

setOption(name, value)

This method is used to set the value of a nxpython option. An option can be set at any time of the design flow.

...

The available options are:

“00”, “01”, “10”

“001”, “010”, “100”

...

...

project.setOption('MappingEffort', 'Medium')

setOptions(options)

This method allows user to set the values of several nxpython options. The options can be set at any time of the design flow.

...

options = {
	'MappingEffort': 'Medium',
	'AdderToDSPMapThreshold': '12'
}
project.setOptions(options)

setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

This method specifies the data arrival times at the specified output ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

...

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setOutputDelay(getClock('CLK'), 'rise', 1000, 1500, getPorts('dataout[`[0−5]`]'))

setSite(instancePattern, siteName)

This method is used to place a set of register/LUT/Carry instances into a specific TILE site.

...

p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]')#DFF
p.setSite('i_cpt_1|LessThan_L23/lut_0','TILE[5x2]')#LUT LESS_THAN
p.setSite('i_cpt_2|add_L24_stage1','TILE[7x2]')#CY ADD

setTopCellName([library], name)

This method is used to set the name of the HDL top module. If the HDL module is defined inside a library, the name of the library can be passed as the first argument.

...

setVariantName(variant)

This method is used to set the variant of the project. The default value of the variant is 'NG-MEDIUM'.

...

project = createProject()
project.setVariantName('NG−MEDIUM')
project.setVariantName('NG−LARGE')
project.setVariantName('NG−ULTRA')

Anchor
synthesizef synthesizef

synthesize()

This method is used to synthesize the HDL source files and realize the technology mapping against nxpython library.

...

project = createProject()
project.load('native.nym')
project.synthesize()

translateAperture(regionName,horizontal,vertical)

This method is used to move the aperture of a region or of the whole design.

...

project = createProject()
project.translateAperture('SUB_REGION_0',1,2)
project.translateAperture(3,4)

...

Simulation related methods

This section presents the methods related to of the analyzer simulator object. The This object controls the static timing analysissimulation of the design.

...

addTestBench([library], testBench)

This method is used to destroy the analyzer object.

This method takes no argument.

...

add a testBench file. The file can be added to a specific library by passing its name as the first optional argument 'library'. The default library is 'work'.

Arguments:

Example:

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createAnalyzer()
analyzer.launch()
analyzer.destroy()

...

simulator.addTestBench(‘testbench.vhd’)
or
simulator.addTestBench(‘myLib’, ‘testbench.vhd’)

addTestBenchs([library], fileList)

This method is used to run the static timing analysis.

The analyzer computes a maximum of 'searchPathsLimit' paths for each domain, considering only the paths which slack is less than or equal to 'maximumSlack'.

Temperature and voltage can also be supplied to adjust timing values.

When not given, the parameters take their default valuesadd several testbench files. The files can be added to a specific library by passing its name as the first optional argument library. The default library is work.

Arguments:

...

Example:

simulator.addTestBenchs([‘testbench1.vhd’, ‘testbench2.vhd’])
or
simulator.addTestBenchs(‘myLib’, [‘testbench1.vhd’, ‘testbench2.vhd’])

addWave(wave)

This method is used to add a signal which will be displayed in vsim. It is also possible to add all the available waves by passing '*' as argument.

Arguments:

Example:

simulator.addWave(‘*’)
or
simulator.addWave(‘A’)