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Table of Contents

List of

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Figures

NxScope NXscope capture process

NxScope generator NXscope Generator GUI

file name

NxBoard NXboard GUI

NxBoard NXboard GUI scope menu

example 1 functional block diagram

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display caused by an erroneous sample

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NXscope Overview

NxScope NXscope is an embedded logic analyser analyzer enabling you to record samples of your design’s internal signals at the rising clock edge and analyse analyze the results in a waveform viewer.

  • NxScope NXscope implements a NanoXplore IP Core generated by the NxCore NXcore Generator

  • The capture process is controlled by JTAG through the ANGIE USB-JTAG adapter via NxBase2 NXbase2 software or the NxBoard NXboard GUI

  • The results are displayed and analysed analyzed with either of the following tools:

    • The ModelSim Waveform Viewer, using a simplified testbench to read the TXT file generated by the NxCore NXcore generator

    • The GTKWave Waveform Viewer (free software)

Note

Note: The NxScope NXscope logic analyser analyzer is implemented in the proposed user design. As a result, it makes use of the uses the FPGA unit's available logic resources of the FPGA unit (e.g. tile logic and RAM blocks). Make sure all constraints (particularly timing constraints) are met after NxScope NXscope is initiated

 

Anchor
_Figure1
_Figure1

 

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NxScope NXscope IP Core comprises 3 main functional blocks:

  • The Trigger Engine
    A configurable module for detecting the trigger conditions to capture samples

  • The Capture Unit
    A configurable module to store the captured samples

  • The JTAG Interface
    Activates the trigger engine and transfers captured samples to the workstation through the ANGIE USB-JTAG adapter via NxBase2 NXbase2 software or the NxBoard NXboard GUI

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NXscope Features

Trigger Features

  • 1 to 32 trigger input lines

  • Optional trig_immediate input

  • Single or dual sequential trigger conditions

  • Level-based (basic) or level- and edges-based (basic_and_edges) triggers

Capture Settings

  • Capture width: 2 to 240 input lines

  • Capture depth: 2K, 4K, 6K, 8K, 12K, 24K or 48K

  • Programmable number of samples stored before trigger condition

  • Optional windowed capture mode (capture depth is sub-divided in multiple windows)

  • Optionally stores the trigger pulse

  • Optionally stores the Window number, if applicable

  

NxScope NXscope trigger conditions are flexible:

  • Up to 32 trigger lines

  • Single or two-level trigger conditions

  • Basic trigger conditions on ‘0’, ‘1’ or ‘X’ on each one of the trigger lines

  • Edge detection (rising, falling or both) on up to 32 trigger lines

  • User’s defined pre-trigger storage (not available when two-level trigger is selected)

  • Trig on condition(s)

  • Trig immediate (no condition)

  • Up to 240 sampled signals

 

Using NxScope NXscope is typically a 4-step process describes in the sections below.

Step 1: Generate the

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NXscope IP Core

The NxScope NXscope IP Core is generated using the NxCore NXcore Generator tool.

All triggers and data sampling parameters are defined by the user including:

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Info

Note: In the current version, all settings including trigger conditions are static. Any modifications require re-generation of the NxScope NXscope IP Core and design implementation

Step 2: Instantiate the Generated

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NXscope IP Core in your Design

After generating your customised NxScope customized NXscope IP Core, you must instantiate it in your designDesign.

The I/O Input and Output signals to be connected are as follows:

Inputs

Name

Type

Description

CLK

std_logic

User Clock

ENA

std_logic

Enables the clock for all NxScope NXscope internal logic, including trigger and capture. Can be tied to ‘1’ if not used

TRIG_LINES

std_logic_vector

User-defined (1 to 32-bit)

DATA_LINES

std_logic_vector

User-defined (2 to 240-bit)

TRIG_IMMEDIATE

std_logic

Can be optionally used to resume a pending capture when the trigger condition can’t be met. Starts an immediate capture when going high

Outputs

The

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NXscope IP Core outputs can optionally be used

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as

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Status Information.

Name

Type

Description

TRIG_ARMED

std_logic

Can be optionally used to monitor the NxScope NXscope internal status

DONE

std_logic

High when the capture is complete. Can be used as status-bit

FIRST_LEVEL_TRIG_OK

std_logic

High after the first-level trigger condition has been met. Can be used as status - bit to inform about the current state of the analyser analyzer when a two-level trigger is selected and, for example, connected to a LED

CURRENT_CAPTURE_SET

std_logic_vector(3 downto 0)

Available exclusively in “Multiple windows” mode. These 4 bits form a counter that is incremented whenever a new window capture is started. Beyond 15 windows, the counter wraps around. Can be used as status bits to monitor the progress of the capture windows.

JTAG Pins

The captured samples are read by NxBase2 NXbase2 or NxBoard NXboard software via the ANGIE USB-JTAG adapter.

Info

Note: JTAG pins are buried in the NxScope NXscope IP Core there is no need to directly refer to JTAG pins

Step 3: Implement the Design and Generate the Bitstream

  1. Synthesise, Place and Route your design and generate your Bitstream using Impulse or nxpython as described in the Impulse Design Flow manual

  2. Check the reports to ensure timing constraints are met

Step 4: Launch

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NXbase2/

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NXboard and

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NXscope Commands

Using NxBase2 NXbase2 software or the NxBoard NXboard interface, follow these steps:

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See the NxBase2 User Manual for more detailed information about the available NxScope NXscope commands.

Once the data has been captured, an ACSII ASCII file is generated in TXT or VCD format.

You can review the TXT results via a simple testbench in the ModelSim waveform viewer or the VCD results using the free open-source GTKwave waveform viewing software.

Create a Custom

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NXscope IP Core

The NxScope generator is a GUI where you can NXscope Generator interface enables you to define all available parameters of the logic analyzer.

In order to To launch the NxScope generatorNXscope Generator, launch first the NXcore GUI (by typing the “nxcore” “NXcore” command at the prompt, and then, select the “NxScope” “NXscope” icon on the GUI left top side.

The next figure is a screen capture of the NXcore / NxScope generator NXscope Generator GUI. All customizable parameters are available in on this single page.  Anchor_Figure2_Figure2

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When all NxScope NXscope parameters are set, the IP Core can be generated by pressing the « generate » command, in the bottom-right part of the window.

Entity Name

The NxScope generator NXscope Generator generates a VHDL encrypted file. The entity name is entered here. The VHDL path and file name are chosen with the “Generate” (bottom-right of the window).

The entity can then be instantiated in the design as a VHDL component.

The generated VHDL file includes a header (not encrypted) where the user can see the ports port names, modes, and width.

 

Capture Configuration Input line count: integer range 2 to 240

Up to 240 internal signals can be sampled and captured.

 Capture_depth: integer range 2048 to 49152

Defines the capture depth of the DATA_LINES sampled and stored on internal RAM block(s). The maximum depth is 48K.

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Both “Capture_depth” and “Input line count” define the amount of internal RAM to be used by the IP Core, as for example:

  • A single memory block can store up to 2048 x 24-bit words.

  • With 10 RAM blocks up to 24K x 20-bit words can be stored.

 Capture_mode: “Pre-trigger” or “Multiple windows”

This setting allows enables you to assign one or more capture windows to the NxScope NXscope capture memory.

  • Pre-trigger”: the “Capture depth” is used as a single capture windows window that uses the whole depth. In this mode, the user can define the number of samples to be stored before reaching the trigger condition. For example, a 2048-word allows to enables you store N samples before, and 2048-N samples after the trigger condition. Alternately, this mode supports a two-level trigger. In this case, a first trigger condition must be met, then the second (and final) trigger condition starts the data capture.

  • Multiple windows”: the “Capture depth” is divided in into multiple sub-windows allowing multiple captures until filling the complete available RAM. As an example, if “Capture depth” = 2K, the user can define 4 windows of 512 samples. The setting of “Window capture length” defines the length of the sub-windows.

 Window capture length: integer range 64 to 2048

This  setting  allows  to  define setting enables you to define  the length of  the the  capture  windows  when when  “Capture mode” = “Multiple windows”.

 Pre-trigger_

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samples: integer range 0 to capture_depth-1

  • When “Capture mode” is set to “Pre-trigger” and “Multiple level trigger” is “false” it’s possible to sample data before reaching the trigger condition. “Pre-trigger samples” defines the number of samples acquired before the trigger condition is met.

  • If “Multiple level trigger” is set to true, the value of “Pre-trigger samples” is ignored, and the capture starts when the second trigger condition is met.

However, in any mode, the user has still the option to store up to 2 samples to be acquired before triggering, by using the “User data delay” setting.

 User data delay: integer range 0 to 2

Available in all trigger modes, this setting allows to store storage of 0 to 2 samples before meeting the trigger condition. It can be particularly useful in “Multiple windows” mode, or “Pre-trigger” if “Multiple level trigger” is set to true. It allows to capture and visualize up to 2 samples before the trigger condition is met.

Note that this option requires using additional logic resources for implementation.

 Store trigger pulse: Enable or Disable

This setting allows enables you to store the trigger pulse (when the trigger condition is met), so it can appear automatically as an additional additionally captured data_line.

When “Store trigger pulse” = “Enable”, the number of sampled signals is then:

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The user’s defined sampled bits being Input line count -1 downto 0, so the weight (index) of the trigger pulse in the captured flow is “Input line count”.

 Store window number: Enable or Disable

When “Capture mode” is set to “Multiple windows”, the total capture depth is split in into several capture windows. The length of each window is defined with the “Window capture length” parameter.

NxScope NXscope gives the user the ability to store the window number for each partial capture. This option can be helpful for the visualization and identification of the several capture sets.

When “Store window number” is set to “Enable”, four additional bits are stored in the capture memory, giving up to 16 different windows window numbers (can be helpful to clearly identify each capture window when displaying the resulting waveform. The number of signals sampled by NxScope NXscope will be:

o   “Input line count” + 4 if “Store trigger pulse” = “Enable”. In this case, the windows number are stored as:

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o   “Input line count” + 5 if “Store trigger pulse” = 1”. In this case, the windows window number are stored as:

(“Input line count” + 4 downto “Input line count” + 1).

 

Trigger Configuration

Trigger line count: integer range 1 to 32

The trigger lines

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are analyzed to find the trigger

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conditions

 

Trigger mode: “Basic” or “Basic & Edges”

The trigger lines

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are analyzed to find the trigger

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conditions

There are two possible 2 trigger modes:

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Panel
bgColor#EAE6FF
  • Basic
    The values detected for each trigger line are:

    • ‘0’

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    • ‘1’ and

    • ‘Ignore’

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  • Basic &

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  • Edges
    The possible values are

    • ‘0’

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    • ‘1’

...

    • ‘Ignore’

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    • ‘Rising edge’

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    • ‘Falling_edge  and

    • ‘Both edges’

Note

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: Basic & Edges provides more trigger flexibility, but requires

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more logic resources for trigger implementation

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Multiple level trigger: “Enable” or “Disable”

When “Capture mode” is set to “Pre-trigger” the user can define a two-level trigger condition. The analyzer will search first for the first level trigger condition, before searching for the second level and final trigger condition and start the data capture. For this, the “Multiple level trigger” must be set to true, and the “First level trigger value” must be defined by the user.

The NxScope NXscope IP Core output goes from a low state to high when the first trigger condition has been met. 

 

Trigger

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Value

When “Trigger mode” is set to “Basic”, each trigger line will be compared to the following possible values: ‘0’, ‘1’ or ‘Ignore’

When “Trigger mode” is set to “Basic & Edges”, each trigger line will be compared to the following possible values: ‘0’, ‘1’, ‘Rising edge’, Falling Edge’, ‘Both Edges’ or ‘Ignore’

 

First level trigger value:

When”Multiple ” Multiple level trigger” is set to “Enable”, the pre-trigger condition must be specified too.

If this option is disabledisabled, the “First level trigger value” is ignored.

 

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NXscope IP Core Generation:

Once the NxScope NXscope parameters are set, press the “Generate” command icon in the bottom-right part of the window.

A new window appears. It allows you to choose both file name and path.

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A VHDL encrypted file is then generated. A header in clear VHDL (not encrypted) is available. This header appears as comments. It can be used for the component declaration when instantiating the NxScope NXscope IP Core in the design to be analyzed.

 

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NXscope Capture Tools

After compiling the design, the user must send the bitstream to the FPGA and then launch the data capture.

You can launch the capture using the using NxBase2 NXbase2 or NxBoard NXboard as described in the sections below.

Launch Sample Capture with

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NXbase2

Use nxbase2NXbase2_cli to run the following commands:

  1. Load the bitstream:

    Code Block
    >> nxbase2NXbase2_cli –s /bitstream_path/bitstream_name.nxb
  2. Launch a capture*:

    • For a (ModelSIM) TXT file

      Code Block
      >> nxscopeNXscope capture dump.txt 50E6 
    • For (GTKWave) VCD file

      Code Block
      >> nxscopeNXscope capture dump.vcd 50E6

*Where 50E6 is the frequency of the sample clock for the design (50 * 10**6 = 50 MHz in this case).

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If “immediate” = 1, the predefined trigger condition is ignored and the acquisition starts immediately

Launch Sample Capture with

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NXboard

At the prompt, launch the following command:

Code Block
>>NxBoard>>NXboard

NxBoard NXboard GUI appears:

Anchor
_Figure4
_Figure4
 

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After the FPGA has been loaded with the bitstream containing the NxScopeNXscope, select the “Scope” icon (left side of the GUI) to enter the capture command.

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Note that the value given to the “Capture Frequency” is taken in into account only for the VCD file generation if this format is chosen.

A message will be issued after the captured data has been stored in the specified file.

 

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NXscope results format:

NxScope NXscope can store the captured results in two possible formats:

  • .txt: preferred format for waveform display on ModelSim/QuestaSim

  • .vcd: preferred format for waveform display on GTKwave – free software

 

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NXscope Capture Sequence

After configuring the FPGA with the bitstream containing the NxScope NXscope IP Core and before launching the NxScope NXscope capture command, the “DONE” and ‘TRIG_ARMED” output pins of the NxScope NXscope IP Core are low. The IP Core is waiting for a command.

When launching the capture, the “TRIG_ARMED” goes high. The NxScope NXscope IP Core is waiting for the trigger condition(s).

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After filling the assigned internal RAM the capture stops and the “DONE” output goes high. At this time, the NxBoard NXboard / NxBase2 NXbase2 software starts reading the captured data via the ANGIE USB-JTAG adapter. A message appears on the console to inform that reading is complete.

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Note

If the trigger condition is not met, the acquisition never resumes, and the software (NxBase2 NXbase2 or NxBoardNXboard) stays waiting indefinitely.

In order to To prevent such a situation, it’s possible to use the optional input pin of the NxScope NXscope IP Core “TRIGGER_IMMEDIATE”. This pin must be tied to a low state in a normal situation. When it goes high, an immediate acquisition is started, ignoring the trigger condition(s).

 

 

 

 

 

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NXscope capture and display example

Launch

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NXbase2/

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NXboard and

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NXscope commands

In order to To sample the data lines, you must use the Angie USB-JTAG adapter, and the NxBase2 NXbase2 software or NxBoard NXboard GUI.

The bitstream must first be loaded before the capture can be launched as specified in the previous section.

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Once the data has been captured, an ACSII file is generated (.TXT or .VCD). The results can be then analyzed in the ModelSim waveform viewer (.TXT result file), with a simple testbench or with the free GTKWave waveform display software using the .VCD result file.

 

Display and analysis of the captured results

Open ModelSim and launch the testbench simulation

As mentioned previously the ModelSim waveform viewer can be used to visualize and analyze the captured results (.TXT result file).

The. TXT file generated with the sampled results is read by a simple testbench, to be converted to graphic waveforms.

Have a look on See the following example:

Code Block
languagevhdl
library ieee;

use ieee.std_logic_1164.ALL;

library STD;

use STD.textio.all;

use ieee.std_logic_textio.all;

 

entity TB_NxScopeNXscope is

end TB_NxScopeNXscope;

 

architecture TB_ARCHI of TB_NxScopeNXscope is

 

signal CLK       : std_logic;

signal SAMPLES: std_logic_vector(25+1 downto 0);

 

signal DIN: std_logic_vector(10 downto 0);

signal DIN_VALID : std_logic;

signal DOUT: std_logic_vector(11 downto 0);

signal DOUT_VALID: std_logic;

 

signal TRIG_PLS  : std_logic;

 

Libraries declarations

 

 

Testbench entity

 

 

Signals declaration

Code Block
languagevhdl
begin

 

process

file RESULT      : text;

variable LINE_VAR: line;

variable DVAR: std_logic_vector(25+1 downto 0);

begin

   file_open(RESULT, "dump.txt", read_mode);

   while not(endfile(RESULT))  loop

      wait until rising_edge(CLK);

      readline(RESULT, LINE_VAR);

      read(LINE_VAR, DVAR);

      SAMPLES <= DVAR;

   end loop;

   file_close(RESULT);

   wait;

end process;

 

 

Main process reading the “dump.txt” result file

 

Values read are assigned to the “SAMPLES” signal

Code Block
languagevhdl
process  begin

   CLK <= '0';  wait for 10 ns;

   CLK <= '1';  wait for 10 ns;

end process; 

 

DIN        <= SAMPLES(10 downto 0);

DIN_VALID  <= SAMPLES(11);

DOUT       <= SAMPLES(23 downto 12);

DOUT_VALID <= SAMPLES(24);

 

TRIG_PLS   <= SAMPLES(25);

 

end TB_ARCHI;

 

Clock waveform

 

“SAMPLES” is split to into several signals to restore the original ones

The user can then set its own waveform settings.

 

Open the .VCD result file with GTKWave and view/analyze the captured results

GTKWave is a free waveform display software. It allows enables you to display the waveform of signals that are stored in .VCD format.

Please, refer to the GTKWave documentation for detailed information.

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NXscope IP Core configuration examples

The following shows three different examples of NxScope NXscope configurations.

 

Example 1: 12K x (25 + 1) capture with 50 samples pre-trigger condition

Number_of_trig_lines = 4

Input line count = 25

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Functional block diagram

 

Anchor
_Figure6
_Figure6

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Example 2: 24K x (33 + 1) capture (2 samples pre-trig cond)

Number_of_trig_lines = 6

Input line count = 33

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Functional block diagram

 

Anchor
_Figure7
_Figure7

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5.3    Example 3: 8K x (42 + 1 + 4) capture (2 samples pre-trig cond)

 

Number_of_trig_lines = 8

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Functional block diagram

 

Anchor
_Figure8
_Figure8
 

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6 Known issues

Erroneous single sample in the captured stream:

 

Depending on NxScope NXscope settings, a dummy sample can be inserted into the captured stream.

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This sample can appear anywhere in the waveform. FortunatellyFortunately, it’s easy to recognize, and it must be ignored.

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NanoXplore is working to correct this problem as soon as possible.

  

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7 How to order a

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NXscope license

 

NxScope NXscope license is not included in the “”nxmap” “nxmap” software. A separate license must be ordered.

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