Feature

• NG-ULTRA is now available on NX design suite tools NxDC/Nxpython

• Timing Driven option is now available. Please refer to “Best Practice” manual.

Static Timing Analysis (STA)

• Nanoxplore Design Contraints (NxDC) : The following python methods are compliant with NxMap:

  • reportTiming (from registers register to registersregister)

  • CreateClock

  • CreateGeneratedClock

  • SetClockGroup

  • SetFalsePath

  • SetMulticyclePath

  • SetMin/MaxDelay

  • SetInput/OutputDelay

  • SetCaseAnalysis

  • SetAnalysisConditions

  • DevelopCKGs

Constraint

• Constrainpath DSP register: Source or destination register can be inside a DSP

• Lowskew management: lowskew signals can be managed using getLowskewSignals, setGCKCount and limiLowskew methods in order to exceed +20 lowskew signals

• Method

• Previous Python STA methods are kept compatible on this version but will be deprecated in next version. All STA constraints are translate into the new format inside log.

• STA can be saved in .nym projects setting 'SaveTiming' option to 'Yes'

GUI

• New interface

  • Docks can be move independently on main windows or move apart

  • Docks:

    • Interpreter allow to write python method

    • Dashboard show a reduction of global floorplan view

    • Selection:

      • Selection tab on all elements with filter bound to “Command” selection.

      • Detailed informations on selected elements

        • Select paths: Provide STA informations on the selected path

        • Select instance:

          • Hierarchy level, Region and Module informations

          • Source file and TILE/CGB location

          • Input/output net name

          • Configuration informations

      • Dynamic SetSite management

    • Regions :

      • Show all Regions and Modules with utilization details

      • Create/Resize/Delete Region dynamically

      • Assign Module to a new Region dynamically

      • Clipboard and generate python file with all Region/Module/SetSIte/(DSP/RAM)Location

  • Command:

    • Select paths :

      • Longest/Shortest path selection

      • New clock domain selection

      • Detail STA report on selected path

  • Floorplanning overview (Prepared):

    • Refresh fabric element dispatch after Region/Module modification in order to visualized new floorplanning

• Information given in nxmap can be copy/past from GUI

Python method

• Constrainpath: Source and destination registers inside a same DSP can be attached independently by different constrainpath.

• exportSites: to export placement constraints for LUTs, DFFs, RAMs, RFs, DSPs, CYs of the design

• Method rejectLowskew: to avoid routing signals into lowskew treeMethod . Can replace NX_BD instanciation.

• addBlackBox: to add preplaced IP into design

• NxRegExp update:

p.addFalsePath('getPort(cpt_in[0])','getRegisters(“cpt_in_p_reg\[[0-3]\]”)') => p.addFalsePath(getPort(

...

“cpt_in[0]

...

”),getRegisters(

...

“cpt_in_p_reg['[0-3]']

...

”))

Primitive

• Header: Get NxMap release information in nxLibrary files headers

• SERDES primitives : implement “locked” in generics

Logging

• Module instance reporting

Report

• Reports have new format and more informations

• Hierarchy.rpt: Indicates memories and operators used n each design moduleinformation in each hierarchy level

• Infinite loop reporting: Logs give the net + the file and line

• Register optimizationRegisters.rpt: Get information about optimized registers in registers.rpt

• Module and Region in STA report: Get the associated region information on Region and module associate to each element in STA detailed path

• DFF reporting registersSummary.rpt : Get type of the DFF (DFF/DFR) in registersSummary.rpt + get number of DFF by primitive (FE/DSP/RAM/PAD)

• Operator in LUT.rpt:

  • Adders mapped in LUT appear in reports

  • Automatic LUT and logic level evaluation is given for all operator

• addFalsePath : all registers, if source or target is empty, number of found registers is *

• Design Constraints : report all STA constraints

• NX_DFF primitive in the design is now reported

Netlist

• Header: Get NxMap release information in a header

Tool

• Saved STA: STA can be saved in .nym projects setting 'SaveTiming' option to 'Yes'NX_HSSL_L: netlist generation is now compliant with NX_HSSL_L primitive

• NX_PLL_L: use_pll generic is now mapped

Tool

• Large multiplication in ULTRA: compliance with much larger multiplication using CY for adders for better STA optimization

• ULTRA renaming: ULTRA is renamed in ULTRA1 and ULTRA2 in ULTRA

• NXScopeV2: New Scope IP is compliant and can be used in NG-ULTRA

• Compilation in NX library: NX is a forbidden library to compile

Bug

...

• addMappingDirective for a RAM in DFF : Tool was not able to map a RAM into DFF if infered memory is compiled in a library

Primitive

Logging

• NX_DFF reporting : NX_DFF primitive in the design is now reported

• addFalsePath all registers, if source or target is empty, number of found registers is *

Netlist

• NX_HSSL_L: netlist generation is now compliant with NX_HSSL_L primitive

• NX_PLL_L: use_pll generic is now mapped

Tool

• Attributes: attributes were ignored in some cases + log during synthesis added

• Differential pad with suffix : pads with suffixes like “_DQS_SWDI” were not able to be configured in differential mode

• DSP registers with asynchronous reset : asynchronous reset DFF cannont can’t be merged in DSP

• PrePlace_IP : preplace_IP allows to import IP already constraint in order to replace automatically matching instances.

NXCore

• NXCore IPs can be update independently of nxmap.

• New interface

• NXScopeV2: New NXScope IP is compliant with all FPGA

Bug

• NXScopeV2: Generation issue. Update will be provide on our website.

• NXScopeV1: NXScope is not compliant with NG-ULTRA

• SDF : NX_RAM in ECC Fast does not get tipd for ACKD/BCKD

• Vcore voltage given in SDF files and STA files in NG-ULTRA are NG-MEDIUM/LARGE core value.