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Comment: add preAnalyze

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Table of Contents
minLevel1
maxLevel7

General

destroy()

This method is used to destroy the analyzer object.

...

Code Block
languagepy
analyzer = project.createAnalyzer()
analyzer.launch()
analyzer.destroy()

preAnalyze()

This method is used to pre-analyze and check if each timing constraint is valid or not.

This method takes no argument.

Example:

Code Block
languagepy
analyzer = project.createAnalyzer()
analyzer.createClock(target=getPort('clk'),name='clk', period=10.0)
analyzer.preAnalyze()

launch(parameters)

This method is used to run the static timing analysis.

...

When not given, the parameters take their default values.

Arguments:

Name

Type

Description

parameters

dictionary

Keys are the names of the parameters to set (see following table), values must match the type specified.

Available Parameters:

Name

Type

Description (Default value in bold)

searchPathLimit

unsigned

maximum number of paths computed for each domain.

(default value is 10)

maximumSlack

integer

maximum reportable slack in ps.

(default is unlimited)

conditions

string

 

‘bestcase’ : Voltage = typical core voltage + 0.1V

Temperature = -40°C

'typical’ : Voltage = typical core voltage

Temperature = 25°C

‘worstcase’ : Voltage = typical core voltage - 0.1V

Temperature = 125°C

Example:

Code Block
languagepy
analyzer = project.createAnalyzer()
parameters = {	'searchPathLimit': 15, 'conditions': 'worstcase'}
analyzer.launch (parameters)
parameters = {	'searchPathLimit': 15, ‘maximumSlack’ : 500, 'conditions': 'worstcase' }
analyzer.launch (parameters)
Note

The project step must be at the minimum “prepared” to run this method.

preAnalyze()

This method is used to analyze timing constraints without running the static timing analysis.

...

Code Block
languagepy
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
analyzer = project.createAnalyzer()
analyzer.preAnalyze()

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project. This constraint is used by timing driven algorithms and static timing analysis.

...

Code Block
breakoutModewide
languagepy
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name ='clk', period = 8, rising = 0, falling = 4)
project.developCKGs()
project.createGeneratedClock(source = 'getWFGOutput(wfg_clk[1])', target= 'getRegister(data_reg[0])', name='clk1_div2', divideBy = 2)

setAnalysisConditions(conditions = 'conditions')

This method is used to specify the chip conditions for the static timing analysis. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

conditions

string

Specifies the conditions for static timing analysis.

Example:

Code Block
languagepy
project.setAnalysisConditions(conditions = 'worstcase')

setCaseAnalysis(value = 'value', netList = netList)

This method is used to specify a constant logic value to the given tests. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

value

string

The valid constant. Values can be ‘0' or '1’

netList

string

Specifies how to get one or several nets. A valid argument can be: getNet(net_name), getNets(net_name_expression), getPort(port_name), getPorts(port_name_expression)

Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered. The constant value is propagated through the network as long as a controlling value for the traversed logic is at the constant value.

Example:

View file
nameInvalid file id - UNKNOWN_MEDIA_ID

...

In the example above, two clocks (clk[0] and clk[1]) are connected to the inputs of the multiplexer, but only clk[1] is propagated through the output after setting the constant value on the selection signal (sel).

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.setCaseAnalysis(value = '1', netList = getNet(sel))

clearTimingConstraints()

This method is used to clear all design constraints from the current project.
Cleared constraints can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

...

Code Block
p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.clearTimingConstraints()

Clock Creation

createClock( target = ‘target', name = ‘name’, period = ]0, ], rising = [0,period[, falling = ]rising, rising+period] )

This method is used to create a clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis. By default, the unit defined is in nsin ns.

Note

Clock creation creates a new starting point.

Arguments:

Name

Type

Description

target

string

Mandatory. The argument that specifies how to get a clock related point. A valid argument can be: getPort(port_name), getRegisterClock(register_name) or getRegister(register_name), getClockNet(clock_net_name).

name

string

Optional. User clock name of the created clock, default name is target_str

period

float

Mandatory. Period for the clock waveform. Must be positive, default value is period/2

rising

float

Mandatory if falling is defined. Otherwise, it is optional. Rising edge for the clock waveform. The range is defined as [0, period[ The default value is 0.

falling

float

Optional. Falling edge for the clock waveform. The range is defined as ]rising, rising + period]. The default value is period/2.

Examples:

...

In the example above, to define a 100MHz clock for net “Clk”, the following three commands are equivalent :

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getRegisterClock(reg1)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getPort(Clk)', name = 'Clk', period = 10)
or 
project.createClock(target = 'getClockNet(Clk)', name = 'Clk', period = 10, rising = 0, falling = 5)

createGeneratedClock(source = ‘source', target = ‘target’, name = 'name', key = value)

This method is used to create an internal generated clock constraint at a timing point. This constraint is used by timing driven algorithms and static timing analysis.

Note

Generated Clock creation keeps the same clock path starting point than the source clock.

Arguments:

Name

Type

Description

source

string

Mandatory. Specifies how to get source clock related point. A valid argument can be: getClock(clock_name), getPort(port_name), getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name), getWFGOutput(wfg_name)

target

string

Mandatory. Specifies how to get a clock related point. A valid argument can be: getRegisterClock(register_name), getRegister(register_name), getClockNet(clock_net_name)

name

string

User clock name of the generated clock

Parameters for computing clock wave of generated clock from master clock are described below:

Key

Type

Description and value

multiplyBy

int

Period multiplication factor. The value must be greater or equal to 1. Default value is 1

divideBy

int

Period division factor. The value must be greater or equal to 1. Default value is 1

dutyCycle

int

Duty cycle of clock period. The range must be from 1 to 99. Default value is 50.0

phase

unsigned

The range must be from 0 to 359

invert

boolean

Invert the clock signal (~ phase = 180)

offset

float

Offset for rising edge

edges

int list

Specifies the edges of the master clock to use in defining transitions on the generated clock. List in non-decreasing order. Mutually exclusive with 'multiplyBy' or 'divideBy'

edgeShift

float list

Shifts the edges of the generated clock by the specified values relative to the master clock. Mutually exclusive with 'multiplyBy' or 'divideBy'

Note

Frequency-based and edge-based relationships are mutually exclusive.

Examples:

...

In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. However note that the "clk_reg" is driven by the falling edge of master clock, the relation between the master clock and the generated clock is shown in the diagram below:

View file
nameInvalid file id - UNKNOWN_MEDIA_ID

...

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.createClock(source = 'getPort(Clk)', name = 'Clk', period = 10)
project.createGeneratedClock(source = 'getRegisterClock(clk_reg)', target = 'getRegisterClock(reg2)', name = 'clk1', divideBy = 2)
or 
project.createGeneratedClock(source = 'getClock(Clk)', target = getRegisterClock(reg2)', name = 'clk1', edges = [2, 4, 6])

...

The diagram of the above command would be:

...

Clock Relationship

setClockGroup(group1 = ‘group1', group2= ‘group2’, option = 'option’)

This method is used to specify which clocks are not related. This constraint is used by timing driven algorithms and static timing analysis. 

A clock cannot be in a different group from itself.

Arguments:

Name

Type

Description

group1

string

Mandatory. Specifies how to get a group of clocks. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name) and getClocks(name_expression).

group2

string

Mandatory. Same as the argument "group1"

option

string

Mandatory. A valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.createClock(name ='clk1', period = 2.7, target= 'getRegister(UUT1\|Gen_seq[2].seq_i\|temp_reg[13])')
project.createClock(name = 'clk2', period = 5, rising = 0, falling = 2, target= 'getClockNet(CLOCK[2])')    
project.setClockGroup(group1 = 'getClock(clk1)', group2 = 'getClock(clk2)', option = 'exclusive')

Delay Path

setMaxDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

target

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required maximum delay value in ns for specified paths.

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.setMaxDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', delay = 3.9)
project.setMaxDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)         
project.setMaxDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 4.0) 
project.setMaxDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)  
project.setMaxDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

setMinDelay(source = ‘source', target = ‘target’, delay = 'delay’)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Specifies how to get a timing path starting points. A valid timing starting point can be either an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

target

string

Specifies how to get a timing path ending points. A valid timing ending point can be either an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

delay

float

The required minimum delay value in ns for specified paths.

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.setMinDelay(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[23]')', target = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[22]')', delay = 1.2)
project.setMinDelay(source = 'getPort(cpt_in[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegister(i_cpt_0\|s_cpt_out_reg[0])', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getPorts("cpt_in[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)
project.setMinDelay(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', delay = 8.0)

setMulticyclePath(source = 'source', target = 'target', pathMultiplier = 'pathMultiplier')

This method is used to specify the multicycle path for the timing paths. It is used by timing driven algorithms and static timing analysis.

Arguments:

Name

Type

Description

source

string

Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).

target

string

Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is a register. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name).

pathMultiplier

integer

Mandatory. A value that represents a number of cycles. Must be greater than 1.

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.setMulticyclePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')', pathMultiplier = 2)
project.setMulticyclePath(source = 'getRegisters("i_cpt_0\|s_cpt_out_reg[`[1-3]`]")', target = 'getRegister(i_cpt_1\|s_cpt_out_reg[1])', pathMultiplier = 2)
Note

This method is only available for path(s) whose source and target registers are clocked by the same clock!

setFalsePath(source = ‘source', target = 'target’)

This method is used to specify the false path for the timing paths. This constraint is used by timing driven algorithms and static timing analysis.

Name

Type

Description

source

string

Mandatory. Specifies how to get a timing path starting points. A valid timing starting point is an input port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),  getRegister(register_name), getRegisters(name_expression),  getRegistersByClock(clock_name)

target

string

Mandatory. Specifies how to get a timing path ending points. A valid timing ending point is an output port or a register. A valid argument can be: getPort(port_name), getPorts(name_expression),  getRegister(register_name), getRegisters(name_expression),  getRegistersByClock(clock_name)

Examples:

Code Block
breakoutModewide
languagepy
project = createProject()
project.load('routed.nym')
project.setFalsePath(source = 'getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]')', target = 'getRegister('UUT2\|dout_reg[61]')')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegister(cpt_in_p_reg[0])')
project.setFalsePath(source = 'getPort(cpt_in[0])', target = 'getRegisters("cpt_in_p_reg[`[0-3]`]")')
project.setFalsePath(source = 'getPorts("cpt_in[`[0-3]`]")', target = 'getRegistersByClock(clk2)')
project.setFalsePath(source = 'getRegistersByClock(clk1)', target = 'getWFGOutput(i_WFG_0)')

In order to match with all registers, source or target can be set to empty.

IO Delay

setInputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit define in the project, timings are in ns or ps.

Arguments:

Name

Type

Description

clock

string

Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. The valid argument is getClock(clock_name).

clockMode

string

Optional. Specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". Default value is rise.

min

float

Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0.

max

float

Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0.

ports

string

Mandatory. Specifies how to get a list of input pads. A valid argument can be: getPort(port_name), getPorts(name_expression).

Examples:

Code Block
project = createProject()
project.load('routed.nym')
project.createClock(target = 'getClockNet(CLK)', name = 'clock',period = 8)
project.setInputDelay(clock = 'getClock(clock)', clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)')

setOutputDelay(clock = ‘clock', clockMode = ‘clockMode’, min = ‘min’, max = ‘max’, ports = 'ports’)

This command specifies the data required times at the specified output ports relative to the clock. The clock must refer to a clock defined in the design. This constraint is used by timing driven algorithms and static timing analysis. Depending on the unit defined in the project, timings could be in ns or ps.

Arguments:

Name

Type

Description

clock

string

Mandatory. Specifies how to get a clock specified. A valid clock should be a clock created by command createClock. A valid argument can be: getClock(clock_name).

clockMode

string

Optional. Specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall". The default value is “rise”.

min

float

Optional. Applies value as minimum data delay, it refers to the longest path. The default value is max if the max is defined, otherwise it is set to 0.

max

float

Optional. Applies value as maximum data delay, it refers to the shortest path. The default value is min if the min is defined, otherwise it is set to 0.

ports

string

Mandatory. Specifies how to get a list of input pads. A valid argument can be:getPort(port_name), getPorts(name_expression).

Examples:

Code Block
languagepy
project = createProject()
project.load('routed.nym')
project.createClock(target = getClockNet('CLK'), name = 'CLK', period = 8)
project.setOutputDelay(clock = 'getClock('CLK'), clockMode = 'rise', min = 1, max = 1.5, ports = 'getPort(RST)')

Report Request

removeTimingConstraint(id)

This method is used to remove a timingconstraint from the current project.
Remove constraint can be clocks, generated clocks, derived clocks of PLLs and WFGs, input delays, output delays, clock groups, analysis case, false paths, multicycle paths, min delay paths, and max delays paths.

Arguments:

Name

Type

Description

id

unsigned

The id of the timing constraint to remove

Example:

This method is used before launching a Static Timing Analysis or using TimingDriven:

Code Block
p.createClock(target=getClockNet('clk1'),name='clk1',period=20.000,rising=0,falling=10.000) #Clk1 is created with 50 MHz frequency
p.removeDesignConstraint(1)
p.createClock(target=getClockNet('clk1'),name='clk1',period=40.000,rising=0,falling=20.000) #Clk1 is now with 25 MHz frequency

addReportTimingRequest(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path.

Timing log files will only contain paths found between sources and targets from these queries.

Arguments:

Name

Type

Description

source_reg

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : getRegister(register_name), getRegisters(name_expression)

target_reg

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: getRegister(register_name), getRegisters(name_expression)

Example:

This method should be launched after creating an Analyzer, as follow :

Code Block
Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportTimingRequest(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.launch()

reportTiming(source = ‘source_reg', target = 'target_reg’)

This method gives the shortest and the longest delays of a path.

...

Timing log files will only contain paths found between sources and targets from these queries.

Arguments:

Name

Type

Description

source_reg

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can only be a register : getRegister(register_name), getRegisters(name_expression)

target_reg

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: getRegister(register_name), getRegisters(name_expression)

Example:

This method should be launched after creating an Analyzer, as follow :

Code Block
Timing_analysis = p.createAnalyzer()
Timing_analysis.ReportTimingPath(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')

addReportPathRequest(source = ‘source_pin', target = 'target_pin’)

This method gives the shortest and the longest delays of a path. This constraint is used by timing driven algorithms and static timing analysis.

Timing log files will still contain all paths. In addition, A file is create with shortest and longest paths found between sources and targets from each query.

Arguments:

Name

Type

Description

source_reg

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can be a register or a port : getRegister(register_name), getRegisters(name_expression), getPort(port_name), getPorts(name_expression)

target_reg

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be: getRegister(register_name), getRegisters(name_expression), getPort(port_name), getPorts(name_expression)

Example:

This method should be launched after creating an Analyzer, as follow :

...

Note

It is not possible to report a clock path with this method. Rather use reportTiming.

reportPath(source = ‘source_pin', target = 'target_pin’)

This method gives the shortest and the longest delays of a path.

...

Timing log files will only contain paths found between sources and targets from these queries.

Arguments:

Name

Type

Description

source_pin

string

Specifies the starting points of the timing paths to be analyzed. A valid argument can be a a pin or a port: getPin(register_name), getPins(name_expression), getPort(port_name), getPorts(name_expression)

target_pin

string

Specifies the ending points or destination objects of timing paths to be analyzed. A valid argument can be a pin or a port: getPin(register_name), getPins(name_expression), getPort(port_name), getPorts(name_expression)

Example:

This method should be launched after creating an Analyzer, as follow :

...

Note

It is not possible to report a clock path with this method. Rather use reportTiming.

removeReportTimingRequest(id)

This method is used to remove a reportTiming from the current project.

Arguments:

Name

Type

Description

id

unsigned

The id of the reportTiming constraint to remove

Example:

Code Block
Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportTimingRequest(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[2])')
Timing_analysis.removeReportRequest(1)
Timing_analysis.addReportTimingRequest(source = 'getRegister(i_cpt_0|s_cpt_out_reg[1])', target ='getRegister(i_cpt_1|s_cpt_out_reg[3])')
Timing_analysis.launch()

removeReportRequest(id)

This method is used to remove a reportPath from the current project.

Arguments:

Name

Type

Description

id

unsigned

The id of the reportPath constraint to remove

Example:

Code Block
Timing_analysis = p.createAnalyzer()
Timing_analysis.addReportPathRequest(source = 'getPin(i_cpt_0|s_cpt_out_reg[1].CK)', target ='getPin(i_cpt_1|s_cpt_out_reg[2].I)')
Timing_analysis.removeReportPathRequest(1)
Timing_analysis.addReportPathRequest(source = 'getPin(i_cpt_0|s_cpt_out_reg[1].CK)', target ='getPin(i_cpt_1|s_cpt_out_reg[3].I)')
Timing_analysis.launch()

...