Table of

...

Figures

Hierarchy report providing user modules detection

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Copyright Notice

All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.

Introduction

This document is intended to guide users of NanoXplore Impulse software through all the steps involved in the design flow and the options available in NanoXplore design suite:

...

All commands described in this document for NXpython can be applied to the provided VHDL examples in example folder.

Package

...

Description

The provided impulse archive contains the following directories:

bin folder contains binary files for each supported Linux distribution
doc folder contains documentation files in pdf format
example folder contains several examples of different projects with design sources in VHDL
lib64 folder contains dynamic libraries and Python modules for each supported Linux distribution and associated Python version
share folder contains additional files (vhdl libraries, simulation libraries, etc...)

Installation

To install impulse, the user needs to unpack nxdesignsuite-VERSION.tar.gz file into the installation directory (e.g. /opt/NanoXplore) using the following command:

...

Where servername is the hostname of the server running the license daemon and 27000 is the port the daemon listens to.

Run

...

NXPython

To run nxpython, use the following command:

...

Code Block

language	py

from nxpython import *

Anchor
nxpythonspec
nxpythonspec

...

NXPython Specification

Command

...

List and

...

Context

Heraafter a The table of below list all available nxpython commands and the context they affect:

Méthod	Project	Synthesize	Place & Route	Bitstream	STA	Simulation
addBank				X
addBanks				X
addBlackBox		X
addDSPLocation			X
addFalsePath					X	X
addFile	X
addFiles	X
addHSSLLocation
addIP	X
addMappingDirective		X
addMaxDelayPath					X	X
addMemoryInitialization				X
addMinDelayPath					X	X
addModule		X
addMulticyclePath					X	X
addPLLLocation			X
addPad		X	X
addPads		X	X
addParameter	X
addParameters	X
addPin		X	X
addPins		X	X
addRAMLocation			X
addRingLocation			X
addRingLocations			X
addVerilogIncludeDirectories	X
addVerilogIncludeDirectory	X
addVlogDefine	X
addVlogDefines	X
addWFGLocation			X
adjustAperture			X
applySdcFile					X
clearBanks			X
clearFabricPrePlaceConstraints			X
clearPLLs			X
clearPads			X
clearPins			X
clearWFGs			X
confineModule			X
constrainModule		X	X
constrainPath		X	X
createAnalyzer					X
createClock					X
createGeneratedClock					X
createObstruction			X
createRegion			X
createSimulator						X
destroy	X
destroyObstruction	X
destroyRegion	X
developCKGs					X
exportAsIPCore	X
exportRegions	X
exportSites	X
generateBitstream				X
generateSTANetlist	X
getAnalyzer	X
getDirectory	X
getErrorCount	X
getHierInfo	X
getLowskewSignals	X
getProject	X
getRemarkCount	X
getTimingUnit	X
getTopCellName	X
getVariantName	X
getWarningCount	X
initRegister				X
limitLowskew			X
listAvailableLocations	X
load	X
modifyPad	X
modifyRegion			X
place	X
progress	X
printError	X
printHierInfo	X
printRemark	X
PrintText	X
PrintWarning	X
rejectLowskew	X		X
removeFile	X
removeFiles	X
removeSoftModules	X
reportDesignComplexity	X
reportInstances	X
reportLowskewSignals	X
reportPorts	X
reportRegions	X
reportRegisters	X
resetTimingConstraints	X
route	X
save	X
setAnalysisConditions					X
setAperture			X
setCaseAnalysis					X
setClockGroup					X
setDescription	X
setDeviceID				X
setDirectory	X
setFalsePath					X
setFocus			X
setGCKCount			X
setInputDelay					X
setMaxDelay					X
setMinDelay					X
setMulticyclePath					X
setOption	X
setOptions	X
setOutputDelay					X
setSite			X
setTopCellName	X
setVariantName	X
synthesize	X
translateAperture			X

General commands

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the impulse module.

createProject([workingDirectory])

This method is used to create an empty project object. The project can then be loaded or built.

...

Code Block

language	py

project = createProject("/path/to/working/directory/")

getErrorCount()

This function returns the number of errors issued during Synthesize, Place and Route flow steps.

...

Output:

Code Block
Errors: 0

getRemarkCount()

This function returns the number of remarks issued during Synthesize, Place and Route flow steps.

...

Output:

Code Block
Remarks: 10

getWarningCount()

This function returns the number of warnings issued during Synthesize, Place and Route flow steps.

...

Output:

Code Block
Warnings: 0

listOptions()

This method lists all available options for current project.

...

Code Block

breakoutMode	wide

| Available project options are:
|   +---------------------------------------------------------------------------+
| | Global                                                                                     |
| +-------------------------------+----------+------------------------------+
| |  Autosave                     |      Yes |                       No Yes |
| | +ClearStack                   |       No |                       No Yes |
| |  Dynamic                      |       No |                       No Yes |
| | +InternalReport               |       No |                       No Yes |
| |  MaxRegisterCount             |     2500 |    Value must be an unsigned |
| | +TimingDriven                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 1/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DefaultFSMEncoding           | OneHot   | Binary OneHot OneHotSafe    
                                                            OneHotSafeExtra |
| |  DefaultRAMMapping            |     AUTO |          AUTO RF RAM RAM_ECC |
| |  DefaultROMMapping            |     AUTO |      AUTO LUT RF RAM RAM_ECC |
| |  DisableAssertionChecking     |       No |                       No Yes |
| |  DisableKeepPortOrdering      |       No |                       No Yes |
| |  DisableRAMAlternateForm      |       No |                       No Yes |
| |  DisableROMFullLutRecognition |       No |                       No Yes |
| |  IgnoreRAMFlashClear          |       No |                       No Yes |
| |  ManageUnconnectedOutputs     |    Error |           Error Power Ground |
| |  ManageUnconnectedSignals     |    Error |           Error Power Ground |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Synthesis (step 2/2)                                                    |
| +-------------------------------+----------+------------------------------+
| |  DisableAdderBasicMerge       |       No |                       No Yes |
| |  DisableAdderTreeOptimization |       No |                       No Yes |
| |  DisableAdderTrivialRemoval   |       No |                       No Yes |
| |  DisableDSPAluOperator        |       No |                       No Yes |
| |  DisableDSPFullRecognition    |       No |                       No Yes |
| |  DisableDSPPreOperator        |       No |                       No Yes |
| |  DisableDSPRegisters          |       No |                       No Yes |
| |  DisableLoadAndResetBypass    |       No |                       No Yes |
| |  DisableRAMRegisters          |       No |                       No Yes |
| |  ManageAsynchronousReadPort   |       No |                       No Yes |
| |  ManageUninitializedLoops     |       No |              No Power Ground |
| |  MappingEffort                |     High |              Low Medium High |
| |  OptimizedMux                 |      Yes |                       No Yes |
| | -SynthesizingEffort           |   Medium |              Low Medium High |
| | -UseSynthesisRetiming         |       No |                       No Yes |
| |  VariantAwareSynthesis        |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 1/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  BypassingEffort              |   Medium |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 2/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -SharingEffort                |   Medium |              Low Medium High |
| | -SharingFanout                |      100 |                          100 |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 3/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  CongestionEffort             |     High |              Low Medium High |
| |  DensityEffort                |      Low |              Low Medium High |
| | -PartitioningEffort           |   Medium |              Low Medium High |
| |  RoutingEffort                |   Medium |              Low Medium High |
| | -UnificationEffort            |      Low |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 4/5)                                                        |
| +-------------------------------+----------+------------------------------+
| |  PolishingEffort              |     High |              Low Medium High |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Place (step 5/5)                                                        |
| +-------------------------------+----------+------------------------------+
| | -DoubleAccess                 |      Yes |                       No Yes |
| | -Permissive                   |      Yes |                       No Yes |
| +-------------------------------+----------+------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 1/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 2/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Route (step 3/3)                                                        |
|   +---------------------------------------------------------------------------+
|   +---------------------------------------------------------------------------+
| | Bitstream                                                               |
| +-------------------------------+----------+------------------------------+
| |  ExhaustiveBitstream          |       No |  No Config Context 
                                                              ConfigContext |
| |  GenerateBitstreamCMIC        |       No |                       No Yes |
| | -MultiBlock                   |       No |                       No Yes |
| |  UnusedPads                   | Floating | Floating WeakPullUp 
                                                               WeakPullDown |
| | -noCfgCtx                     |       No |                       No Yes |
| | -noHeader                     |       No |                       No Yes |
| | -noRun                        |       No |                       No Yes |
| | -noThermalSensor              |       No |                       No Yes |
| | -noWorkaround                 |       No |                       No Yes |
| | -simpleFrames                 |       No |                       No Yes |
| +-------------------------------+----------+------------------------------+

printError(message)

This function is used to print an error message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by ERROR string so it can be easily found.

...

Code Block
ERROR \| It's a trap!

printRemark(message)

This function is used to print a remark message in the impulse output. This includes terminal output and log file if set. An error message is prefixed by REMARK string so it can be easily found.

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Code Block
REMARK \| This is a remark

printText([message])

This function is used to print a message in the impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the impulse output.

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Code Block
\| There is no spoon.

printWarning(message)

This function is used to print a warning message in the impulse output. This includes terminal output and log file if set. A warning message is prefixed by WARNING string so it can be easily found.

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Code Block
WARNING \| The cake is a lie.

setCoreCount(core_count)

This function sets the number of core to use in multi-thread algorithm.

...

Code Block
\| Setting core count to 2

setDirAutoChange(change_project_dir)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Name

Type

Description

change_project_dir

boolean

Change project directory when loading a project file when True (default).

Keep the current project directory when False

...

Code Block

language	py

p = createProject()
setDirAutoChange(False)
p.load('my_path/routed-auto.nym')

setLogDirectory(log_directory)

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Name	Type	Description
log_directory	string	Name of the directory to be created.

...

Code Block
\| Setting log directory to TestLogDirectory

usage()

This method displays application usage.

...

Code Block

language	none

| Usage:
 |   $> nxpython3
 |     will run nxpython3 in interactive mode
 |     
 |   $> nxpython3 file.py
 |     will run the given python file in nxpython3 in batch mode
 |     
 |   options
 |     several options can be used when running nxpython3.
 |     Options must be placed before the file.py argument.
 |     Any option placed after will be passed to the file.py.
 |       -g or -gui        execute nxpython3 with graphical support
 |       -c or -core CORE  execute nxpython3 with maximum core number
 |       -v or -version    display nxpython3 version
 |       -h or -help       display this help

version()

This method displays application version.

...

Code Block
\| Copyright (C) 2010-2020, NanoXplore, All rights reserved

Expected expressions for NXpython methods

NxPython methods get a standardized format for arguments expecting a path.

This section describes the expression format specific to NX.

Impacted methods:

The following methods allow regular expressions / wildcard formats in order to match with multiple instances:

...

· getRegisters

· setSite

· …

Maintainability:

It is no longer necessary to escape (with the ‘\’ character) special characters for these methods.

...

However, the old format is still compliant and still operates.

User use:

In a usual way, a copy/paste of a path from a log file works for the constraint.

...

addMappingDirective(getModels(“add_`[1-2][0-9]`u_*”), …)

Project related methods

This section presents the methods related to the project object.

addBank(name, dict)

The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.

...

Code Block

language	py

project.addBank('IOB0', {'voltage': '2.5'})

addBanks(dict)

The method addBanks allows user to configure several banks of the FPGA to be used for configuration of inputs/outputs of the HDL module. addBanks use a dictionary as an argument.

...

Code Block

language	py

ioBanks = { 'IOB0'  : {'voltage': '2.5'}
                  , 'IOB1'  : {'voltage': '2.5'}
                  , 'IOB2'  : {'voltage': '2.5'}
                  , 'IOB3'  : {'voltage': '2.5'}
                  , 'IOB4'  : {'voltage': '2.5'}
                  , 'IOB5'  : {'voltage': '2.5'}
                  , 'IOB6'  : {'voltage': '2.5'}
                  , 'IOB7'  : {'voltage': '2.5'}
                  , 'IOB8'  : {'voltage': '2.5'}
                  , 'IOB9'  : {'voltage': '2.5'}
                  , 'IOB10' : {'voltage': '2.5'}
                  , 'IOB11' : {'voltage': '2.5'}
                  , 'IOB12' : {'voltage': '2.5'}
          }
project.addBanks(ioBanks)

addBlackBox(name, type, mapping, interface)

The method addBlackBox allows users to define customized mapping of certain HDL modules on the specific FPGA blocks and to dispose the interface of the blocks.

...

Code Block

language	py

project.addBlackBox('myMicroCode', 'ROM', 'RF', 'AD(addr),DO(micro),CK(clk)')

addBlackBox() : for Preplaced IP

The idea is to offer the possibility to the user to reuse the result of an impulse flow as an IP in a top design.

...

Among the instances of the ring, some are not supported yet :
PLL, WFG, CR5, SOC_IF, HSSL

addDSPLocation(pattern, place)

This method is used to select the spot in which a DSP should be placed before launching Place step execution.

...

Note
The pattern argument does not support regular expressions

addFalsePath(from_list, to_list)

This method is used to specify the false path for the timing paths. This constraint is used by timing driver algorithms and static timing analysis.

...

In order to match with all registers, it is possible to specify empty string ('') for parameters from_list or to_list.

addFile([library], file)

This method is used to add a HDL source file to the project. The file can be added to a specific library by passing its name as the first optional library argument. The default library is work.

...

Code Block

language	py

project.addFile('src/simple.vhd')
project.addFile('src/complex.vhd:VHDL_93')
project.addFile('src/simple_verilog.v:VERILOG_95')
or
project.addFile('myLib', 'src/simple.vhd')

addFiles([library], fileList)

This method is used to add several HDL source files to the project. The files can be added to a specific library by passing its name as the first optional library argument. The default library is work.

...

List of HDL source files can be in any order. nxpython will sort them such that dependencies are satisfied.

addHSSLLocation(pattern,location)

This method is used to set the spot in which a HSSL should be set.

...

Code Block
project.addHSSLLocation('i_hssl_esistream\|i_HSSL_ONLY\|i_NX_HSSL_FULL\|ctrl', 'HSSL2')

addMappingDirective(name, type, mapping)

This method is used to add a mapping directive for Synthesis flow step which overrides the default nxpython mapping behavior for a specific HDL module or instance.

...

Note
Mapping a RAM into DFF is only available with getModels but not getInstances.

addMaxDelayPath(from_list, to_list, delay)

This method is used to specify the maximum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMaxDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                        getRegister('UUT2|dout_reg[61]'), 3900)

addMemoryInitialization(name, type, file)

This method is used to specify a file that will be used to initialize a specific memory instance.
Arguments:

...

Code Block
0000 1000 100 10 1

addMinDelayPath(from_list, to_list, delay)

This method is used to specify the minimum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'),
                                     getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1200)

Anchor
addmodule
addmodule
addModule(model, instance, format)

This method is used to add a HDL module definition to the current project that contains all HDL logic elements including within the model given in argument.

...

Note

This method is only available before Synthesize flow.

The model argument expects a regular expression.

addMulticyclePath(from_list, to_list, cycle_count)

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

...

Note
This method is only available for path(s) whose source and target registers are clocked by the same clock !

Anchor
addpad
addpad
addPad(name, parameters)

This method allows user to configure an input/output of the HDL module into specific pad of the FPGA. For the given pad, the configuration has two basic argument (name and parameters).

...

The termination key specifies the output impedance of the pad in Ohms. In differential mode, the impedance is two times the value. It’s specified in Ohms, in the range 30 to 80 Ohms (Default is set to minimum value).

Min and max values depend on the variant and the bank voltage.

Voltage (V)	NG-MEDIUM		NG-LARGE		NG-ULTRA
Voltage (V)	Rmin (Ω)	Rmax (Ω)	Rmin (Ω)	Rmax (Ω)	Rmin (Ω)	Rmax (Ω)
1.2	X	X	X	X	30	84
1.5	X	X	X	X	31	88
1.8	31	85	30	85	32	92
2.5	35	100	34	102	X	X
3.3	X	X	X	X	X	X

Note
Can only be set if terminationReference is set.

...

Code Block

breakoutMode	wide

#LVDS implementation
project.addPad( 'spw_rxd[0]' : {'location': 'IOB19_D16P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT', 'turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_rxs[0]' : {'location': 'IOB19_D17P', standard: LVDS, 'differential': True, 'termination': '50','terminationReference':'VT','turbo': True, 'drive': 'undefined'})
project.addPad( 'spw_txd[0]' : {'location': 'IOB19_D14P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})
project.addPad( 'spw_txs[0]' : {'location': 'IOB19_D15P', standard: LVDS,  'differential': True, 'slewRate': 'Fast', 'drive': 'undefined'})

addPads(pads)

This method is used to configure inputs/outputs of the HDL module into specific pads of the FPGA. The argument is a dictionary that associates the HDL input/output name to a dictionary, which can contain some keys (location, type, weakTermination, slewRate, termination, inputDelayLine, outputDelayLine, differential, terminationReference, turbo) as defined in addPad(name, parameters).

...

If “pads” are not configured of configured incompletely, impulse will randomly place non assigned ports on the FPGA

addPin(name, location)

This method allow user to configure an input/output of the HDL module into specific pin of the embedded FPGA. This method is reserved to embedded variants of FPGA.

...

Code Block
project.addPin('A', 'TUI200')

addPins(pins)

This method allow user to configure inputs/outputs of the HDL module into specific pins of the embedded FPGA. This method is reserved to embedded variants of FPGA.

...

Code Block

language	py

pins = {
	  'A': 'TUI200',
	 'B': 'TUI201'
          }
project.addPins(pins)

Anchor
addparam
addparam
addParameter(name, value)

This method allows user to specify the value of the top design generic parameters.

...

Note
Each parameter must be in the ‘generic’ list of the design top entity. All uninitialized parameters in the design must be set with the value at this step. Already initializerd parameters in the design can be overridden with a new value.

Anchor
addparameters
addparameters
addParameters(parameters)

In case of a large number of parameters, a parameter dictionary can be created consisting of the name of the parameter as a key and its respective value. Both name and value must be string.

...

Note
Each parameter must be in the ‘generic’ list of the design is top entity All uninitialized parameters in the design must be set with the value at this step. Already initialized parameters in the design can be overridden with a new value.

addPLLLocation(pattern, location)

This method is used to set the spot in which a PLL should be set.

...

Code Block

#placing pll0, pll1, pll2, pll3 in different CKGs
project.addPLLLocation('pll0', 'CKG1.PLL1')
project.addPLLLocation('pll1', 'CKG2.PLL1')
project.addPLLLocation('pll2', 'CKG3.PLL1')
project.addPLLLocation('pll3', 'CKG4.PLL1')
#placing a PLL located in a sub-hierarchy of the design
project.addPLLLocation('FIR_MF|CLKG|PLL_20_160', 'CKG4.PLL1')

addRAMLocation(pattern, place)

This method is used to select the spot in which a RAM should be placed. This method must be used and declared before launching Place step execution.

...

Note
The pattern argument does not support regular expressions

addRingLocation(name, location)

This method is used to place an instance in the I/O ring of the FPGA. addRingLocation can be used instead of addPLLLocation, addWFGLocation or addPin.

...

Code Block

language	py

project.addRingLocation('PLL0','CKG1.PLL1')
project.addRingLocation('WFG_3','CKG4.WFG_C1')

addRingLocations(dictionary)

In case of a large number of instances to be placed in the I/O Ring, a dictionary can be created consisting in the name of the instance as a key and its association location. Both name and location must be string.

...

Code Block
rings = { 'PLL0' : 'CKG1.PLL1', 'PLL1' : 'CKG2.PLL1', 'WFG_0' : 'CKG1.WFG_C1', 'WFG_1' : 'CKG2.WFG_C1' } project.addRingLocations(rings)

addVerilogIncludeDirectory(directory)

This method is used to add an extra directory containing Verilog files to the project. This is used when the included files are external to the working directory.

...

Code Block

language	py

project.addVerilogIncludeDirectory('include’)
or
project.addVerilogIncludeDirectory('../lib’)

addVerilogIncludeDirectories(directoryList)

This method is used to add several extra directories containing Verilog files to the project. This is used when the included files are external to the working directory.

...

Code Block
project.addVerilogIncludeDirectories(['include’, ‘../lib’])

addVlogDefine(name,value)

This method is used to add a parameter definition for Verilog files.

...

Code Block

language	py

project.addVlogDefine('G_DATA_SIZE’,'8')

addVlogDefines(dictionnary)

This method is used to add parameters definition for Verilog files.

...

Code Block

language	py

project.addVlogDefines({'G_DATA_SIZE’:'8','G_ADDR_SIZE’:'16'})

addWFGLocation(name, location)

This method is used to set the spot in which a WFG should be set.

...

Code Block

language	py

project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)

adjustAperture(regionName, above, left, right, below)

This method is used to move the aperture of a region or the whole design.

...

Code Block

language	py

project.setAperture(6,8,14,12)
project.ajustAperture(2,3,2,2)
p.createRegion('region_0',7,8,9,10)
project.ajustAperture('region_0',2,3,2,2)

applySdcFile(filePath)

This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.

...

Code Block

language	py

project.applySdcFile(./sdc_directory/constraints.sdc)

clearBanks()

clearBanks() method remove all bank specification previously added in the project.

...

Code Block

language	py

project = createProject()
project.addBank('IOB0', {'voltage': '2.5'})
project.clearBanks()

clearFabricPrePlaceConstraints(regionName)

Clears all preplacing constraints for fabric elements. It removes the impact of the following constraints:

...

Code Block
project = createProject() project.addRAMLocation('module0\|RAM', 'CGB[3x2]') project.clearFabricPreplacedConstraints() project.addRAMLocation('module0\|RAM', 'CGB[4x2]')

clearPLLs()

clearPLLs() method remove specification and location for PLLs previously added in the project.

...

Code Block

language	py

project = createProject()
project.addPLLLocation('pll_0', 'CKG2.PLL1')
project.clearPLLs()

clearPads()

clearPads() method remove all inputs/outputs of the HDL module previously configured into specific pads of the FPGA.

...

Code Block

breakoutMode	wide
language	py

project = createProject()
pads = {
	'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination': 'PullUp', 
          'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 'differential': False, 
         'turbo': True}
project.addPads(pads))
project.clearPads()

clearPins()

clearPins() method remove all inputs/outputs of the HDL module previously configured into specific pins of the embedded FPGA

...

Code Block
project = createProject() pins = { 'A': 'TUI200', 'B': 'TUI201' } project.addPins(pins) project.clearPins()

clearWFGs()

clearWFGs() method remove specification and location for WFGs previously added in the project.

...

Code Block
project = createProject() project.addWFGLocation('wfg_0', 'CKG2.WFG_M3) project.clearWFGs()

Anchor
confinemodule
confinemodule
confineModule(name, region)

This method allows to confine a module into a user defined region of the FPGA.

...

Note

The module name generated by nxpython automatically starts incremental numbering with ‘-1’.

‘-0’ numbering will not be recognized in name argument when using confineModule('name-0', ‘region’).

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a HDL module into a specific region. The aim of constrainModule is to provide a unique and simple function to perform the whole region driven flow described in Creating and handling regions section.

...

Note
The Creating and handling regions flow using the three methods addModule(), createRegion() and confineModule() is still available.

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

This method constrains a virtual module into a specific region. The aim of this function is to identify source and destination registers in order for all logic elements (LUT, carry) between these registers to be placed into a region created with the regionName argument.

...

Note
The difference between constrainModule() and constrainPath() id the first one is used to constrain at instance level whereas the second one allows to constrain at register to register level

createAnalyzer

If a targeted design is already routed, user can launch static timing analysis by creating a timing analyzer.

...

Code Block
project = createProject() project.load('/home/user/example/vhdl/simple/routed.nym') analyzer = project.createAnalyzer()

createClock(target, name, period, [rising, falling])

This method is used to create a clock constraint of a timing point. This constraint is used by timing driver algorithms and static timing analysis.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getRegisterClock(reg1'), 'clk', 10000)
or
project.createClock(getPort(Clk'), 'clk', 10000)
or
project.createClock(getClockNet('Clk'), 'clk', 10000, 0, 5000)

createGeneratedClock(source, target, name, relationship)

This method is used to create an internally generated clock constraint at a timing point. This constraint is used by timing driver algorithms and static timing analysis.

...

The relationship generated by above command is:

Anchor

	Figure8
	Figure8

...

createObstruction(name, column1, row1, column2, row2)

This method is used to create an obstruction object which will be removed from impulse resources for Place & Route steps.

...

Code Block
project = createProject() project.load('synthesize.nym') project.createObstruction('obstr', 10, 2, 24, 6)

Anchor
createregion
createregion
createRegion(name, column1, row1, column2, row2, exclusive)

This method is used to create a region among the FPGA resources where HDL elements will be placed during Place step.

...

Code Block

language	py

project = createProject()
p.createRegion('ALU',      13, 6, 14, 6)
p.createRegion('REGISTER', 22, 6, 23, 6, True)

createSimulator()

This method is used to create a simulator object. A simulator object is used to simulate the project with a specified testbench.

...

Code Block

language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
analyzer = project.createSimulator()

destroyObstruction(name)

This method is used to destroy a given obstruction object.

...

Code Block

language	py

project = createProject()
project.load('synthesize.nym')
project.createObstruction('obstr', 10, 2, 24, 6)
project.destroyObstruction('obstr')

destroyRegion(name)

This method is used to destroy a given region.

...

Code Block

language	py

project = createProject()
project.createRegion('CNTRL',     4, 6,  5, 6)
project.destroyRegion('CNTRL')

developCKGs()

This method automatically creates a generated clock constraint on each output of the PLLs and WFGs in current project.

...

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'),getRegister('data_reg[0]'), 'clk1_div2', {'DivideBy': 2})

destroy()

This method is used to destroy the project.

...

Code Block
Display after destruction Traceback (most recent call last): File "test.py", line 22, in <module> project.display() impulse.error: Invalid Request: Obsolete object

display()

This method is used to open current project in impulse graphic user interface. It can be called several times from the same Python script.

...

Note

nxpython does not need an X11 environment to be run, but the display() method does.

In order to use the display() method, user must add the -gui or -g on the nxpython command line. This option of the tool (not the script) as shown in the following example:

$> nxpython -gui script.py

exportAsIPCore(file, options)

This method is used to export the synthesized design to an IPCore. An IPCOre is a HDL description (at NX components level) that can be given as part of new source design to impulse.

...

Code Block

project = createProject()
project.load('/home/user/example/vhdl/simple/native.nym')
options = { ‘coreName’: ‘IPCore’, ‘encrypt’: ‘All’ }
p.exportAsIPCore(‘IPCore.vhd’, options)
p.synthesize()

exportRegions()

This method is used to export all constrainModule constraints in the console. It can be useful if the user modified the region location or size and want to get new constraints to copy them in the script.

...

Code Block

breakoutMode	wide

project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3, 'TIMER', False)
project.modifyRegion('TIMER', 10, 8, 19, 3)
project.exportRegions()

exportSites(projectVariable,fileName)

This method is used to export all setSite constraints in a file. It can be useful in order to keep all TILE locations.

...

Code Block

breakoutMode	wide

project.exportSites('p','site_constraints.py')

Anchor
generatebitstream
generatebitstream
generateBitstream(file)

This method is used to save the bitstream configuration file to disk. The extension of the target file must be .nxb

...

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.generateBitstream('bitstream.nxb')

generateSTANetlist(filePath,condition)

This method is used to generate routed netlist and SDF file.

...

Code Block

breakoutMode	wide
language	py

project.route()
project.generateSTANetlist(./output_files/routed_sta_file)

setDeviceID(id)

This method is used to change the Device ID in the bitstream header before generating it.

...

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
p.setDeviceID(10) #Set Device ID to 0xA
project.generateBitstream('bitstream.nxb')

getAnalyzer()

This method returns the current analyzer associated to the project to manage STA.

...

Code Block

language	py

project = createProject()
a = project.createAnalyzer()
project.getAnalyzer().launch()

getDirectory()

This method returns the project current directory. This directory is used as root for all relative paths passed as argument of generic functions and/or methods. The default value of the directory is the current working directory.

...

Code Block

language	py

project = createProject()
directory = project.getDirectory()

getHierInfo()

This method returns the detailed hierarchy into a dictionary variable.

...

Code Block
project = createProject() hierarchy = project.getHierInfo() printText(hierarchy)

getLowskewSignals(ignoreTop, showCandidates)

This method is used to get lowskew signals or potential candidates to be lowskew signals. It gives a table of impacted lobes for each lowskew signal

...

Note
This method work only for NG-ULTRA family.

getProject()

This method returns the project object.

...

Code Block

language	py

createProject()
project = getproject()

getTimingUnit()

This method returns the timing unit used in STA.

...

Code Block
printText(project.getTimingUnit())

getTopCellName()

This method returns the name of the top HDL module. If the HDL module is defined inside a library, the name is prefixed by the name of the library followed by a # character.

...

Output:

Code Block
myLib#simple

getVariantName()

This method returns the variant of the project. The default value of the variant is 'NG-MEDIUM'.

...

Output:

Code Block
NG-MEDIUM

initRegister(command, value)

This method is used to write in registers during the generation of bitstream.

...

Code Block
project = createProject() project.load('/home/user/example/vhdl/simple/routed.nym') project.initRegister('SPI_CTRL', '0x01f4003f') project.generateBitstream('bitstream.nxb')

limitLowskew(signal, lobes)

This method is used to limit a lowskew signal to be used in only specified lobes.

...

Code Block
project.limitLowskew('clk_right','Rx1,Rx2,Rx3,Rx4')

listAvailableLocations(name)

This method is used to print all available pads for a bank or for all banks of a variant .

...

Code Block
project.listAvailableLocations() project.listAvailableLocations('IOB10')

load(file)

This method is used to load a previously saved project from disk. The input format (file extension) must be .nym (impulse archive).

...

Code Block

language	py

project = createProject('/home/user/example/vhdl/simple')
project.load('synthesized.nym')

modifyPad(name, parameters)

This method is used to modify the configuration of an existed pad.

...

Code Block

breakoutMode	wide

project.addPad('output[0]',{'location':'IOB10D09P', 'standard': 'LVCMOS', 'drive' :'2mA', 'slewRate':'Slow'})
project.modifyPad('output[0]',{'drive' :'16mA', 'slewRate':'Fast'})

modifyRegion(name, column1, row1, width, height, exclusive)

This method is used to modify the location or the size of an existed region.

...

Code Block
project.constrainModule('\|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12, 19, 3, 'TIMER', False) project.modifyRegion('TIMER', 10, 8, 19, 3)

place()

This method is used to run the place algorithm on a project.

...

Code Block

language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.setOption('TimingDriven', 'Yes')
project.place()

printHierInfo()

This method prints the detailed hierarchy of a project with the module matched and all instances per module.

...

Code Block

language	py

project = createProject()
project.progress('Synthesize', 3)
project.printHierInfo()

progress(step, number)

This method allows to progress through project to a given flow step.

...

Code Block

language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.progress('Place', 3)

rejectLowskew(signal)

This method avoids local lowskew signal to be converted in global lowskew signal.

...

Code Block

language	py

project.rejctLowskew('sub_module0|local_reset')

removeFile(libName, filePath)

This method allows to remove a file from a project.

...

Code Block

language	py

project.addFile('work','sub_modul_0.vhd')
project.addFile('work','sub_modul_1.vhd')
project.removeFile('work','sub_modul_0.vhd')
project.removeFile(sub_modul_1.vhd')

removeFiles()

This method allows to remove files from a project.

...

Code Block

language	py

project.addFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])
project.removeFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])

removeSoftModules(libName, fileList)

This method allows to remove all HDL soft modules from a project.

...

Note
Soft modules can be removed only at Synthesis 2/3 step or before.

reportDesignComplexity(html_file)

This method reports the design complexity, clock domain by clock domain, indicating the logic depth for all paths of the design and illustrates it with a chart in HTML format:

...

The output HTML file looks like:

...

Anchor
reportinstances
reportinstances
reportInstances()

This method reports the instances utilization of the programmed design on the current variant. Three tables are printed. The first one contains values for all types of instances. The instances are grouped by categories:

...

Output:

Anchor

	Figure9
	Figure9

...

reportLowskewSignals(logfile)

This method reports the lowskew signals:

...

Code Block
project.reportLowskewSignals('lowskew_report')

Anchor
reportports
reportports
reportPorts()

This method reports the ports found in HDL source and the ones manually added by user in the project. The report displays the following information:

...

Code Block
project = createProject() project.load('/home/user/example/vhdl/simple/placed.nym') project.reportPorts()

Anchor
reportregions
reportregions
reportRegions()

This method reports occupied resources by HDL elements within every region created in the FPGA.

...

The report displays the amount and percentage placed in the created region:

Anchor

	Figure10
	Figure10

...

resetTimingConstraints()

This method is used to reset all timing constraints for current project.

...

Code Block

language	py

project = createProject()
project.load('/home/user/simple/routed.nym')
project.resetTimingConstraints()

Anchor
route
route
route()

This method is used to run the route algorithm on a project.

...

Code Block

language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/placed.nym')
project.setOption('TimingDriven', 'Yes')
project.route()

Anchor
savefile
savefile
save(file,conditions)

This method is used to save the current project into a impulse archive (.nym), a design netlist (.v or .vhd) or to generate a sdf file containing delays of the design supporting bestcase, worstcase and typical scenarios.

...

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('native.nym')
project.synthesize()
project.save('synthesized.nym')
project.save('synthesized.vhd')
project.route()
project.save(‘routed.vhd’)
project.save('sdf_file_bestcase.sdf','bestcase') #generate a sdf file defining bestcase scenario
project.save('sdf_file_worstcase.sdf','worstcase') #generate a sdf file defining worstcase scenario
project.save('sdf_file_typical.sdf','typical') #generate a sdf file defining typical scenario
project.save(‘routed.sdf’)

setAnalysisConditions(conditions)

This method is used to specify the chip conditions for static timing analysis.

...

Code Block

language	py

project.setAnalysisConditions(WorstCase)

Anchor
setaperture
setaperture
setAperture(column1, row1, column2, row2)

This method is used to define the size of aperture. The default size value is bounded to the Fabric dimensions.

...

Code Block

language	py

project = createProject()
project.load('synthesize.nym')
project.setAperture(10, 2, 24, 6)

setCaseAnalysis(value, net_list)

This method is used to specify a constant logic value to the given tests.

...

Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered.

The constant value is propagated thro

setClockGroup(group1_list, group2_list, option)

This method is used to specify which clocks are not related. This constraint is used by timing driver algorithms and static timing analysis.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet(CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet(CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'),getClock('clk2'), 'exclusive')

setDescription(description)

This method is used to set a description to a project.

...

Code Block

language	py

project = createProject()
project.setDescription('Impulse project for training')

setDirectory(directory)

This method is used to change project directory.

...

Code Block

language	py

project = createProject()
project.setDirectory('./new_dir')

Anchor
setfocus
setfocus
setFocus(column, row)

This method is used to specify the position of the focus.

...

Code Block

language	py

project = createProject()
project.load('synthesize.nym')
project.setFocus(4, 4)

setGCKCount(count)

This method is used to limit the number of GCK at the end of Placing step 2.

...

Code Block

language	py

project.setGCKCount(20)

setInputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500,getPort('RST'))

Anchor
setoption
setoption
setOption(name, value)

This method is used to set the value of a nxpython option. An option can be set at any time of the design flow.

...

Name

Default

Description

'Autosave'

'Yes'

Enable automatic protect save after each flow step.

'BypassingEffort'

'Medium'

Specify the DFF load and reset spreading level into the low-skew network (can be 'Low', 'Medium' or 'High'):

Low: all Load and Resetare sent in low skew

Medium: Impulse choose an effective balance

High: all Load and Reset are routed in common parts ( high routing constraint)

'CMICLatency'

'0'

Additional delay between 2 CMIC scans.

Expressed in number of BSM clock cycles.

'CongestionEffort'

'High'

Specify the routing resources limit per tile (can be 'Low', 'Medium' or 'High'):

Low : less routing constraints but may need further more tiles and CGBs
Medium : balanced routing constraints but may need more tiles and CGBs
High : all routing resources

'Dynamic'

'No'

Refresh view while algorithms are running.

'DefaultFSMEncoding'

'OneHot'

Default encoding of finite state machine (can be 'OneHot', 'OneHotSafe', 'OneHotSafeExtra' or 'Binary'):

Binary: minimum amount of bit is used
OneHot: only one bit changes per state. Others case is not handled.
OneHotSafe: detects invalid state where all bits are ‘0’ and returns to others case.
OneHotSafeExtra: detects any invalid state where all bits are '0' or more than one bit to ‘1’ and returns to others case. Additional logic is implemented.

Example for binary encoding with 3 states:

Code Block
“00”, “01”, “10”

Example for one hot encoding with 3 states:

Code Block
“001”, “010”, “100”

Note

If state encoding is forced by the RTL code with the following example, the FSM is not reported in logs:

attribute enum_encoding of t_state_type : type is "01 10"

'DefaultRAMMapping'

'AUTO'

Default mapping of RAM (can be 'AUTO', 'RF', 'RAM' or 'RAM_ECC').

'DefaultROMMapping'

'AUTO'

Default mapping of ROM (can be 'AUTO', 'LUT', 'RF', 'RAM' or 'RAM_ECC').

'DensityEffort'

'Low'

Specify the instance resources allowed per tile (can be 'Low', 'Medium' or 'High'):

Low: less resources (less routing constraints but may need more tiles and CGBs): 70% is allowed
Medium: well suited resources: 80% is allowed
High: more resources (more routing constraints): 90% is allowed

'DisableAdderBasicMerge'

'No'

Disable carry optimization around adders and subtractors.

'DisableAdderTreeOptimization'

'No'

Disable adder mux reordering and adder tree balancing.

'DisableAdderTrivialRemoval'

'No'

Disable simplification of adder that could fit in 1 or 2 LUTs.

'DisableAssertionChecking'

'No'

Deactivate VHDL assertions.

'DisableDSPAluOperator'

'No'

Disable merge of ALU within inferred DSP.

'DisableDSPFullRecognition'

'No'

Disable inference of DSP.

'DisableDSPPreOperator'

'No'

Disable merge of pre-operator within inferred DSP.

'DisableDSPRegisters'

'No'

Disable merge of registers within inferred DSP.

'DisableRegisterMergeInDspForAdd'

‘No’

Disable merge of registers in DSP when used as adder

'DisableKeepPortOrdering'

'No'

Disable keep port ordering used in source files when generating HDL netlists.

'DisableLoadAndResetBypass'

'No'

Disable load and reset signal bypass on DFF.

'DisableRAMAlternateForm'

'No'

Disable recognition of registered address read port.

'DisableROMFullLutRecognition'

'No'

Disable merge of ROM recognized as LUT with logic.

'DisableRAMRegisters'

'No'

Disable merge of registers within inferred RAM.

‘ExhaustiveBitstream’

‘No’

Can be used to force generation of all configurations and contexts in bitstream (can be ‘No’, ‘Config’, ‘Context’ or ‘ConfigContext’).

'GenerateBitstreamCMIC'

'No'

Generate bitstream with CMIC.

‘InitializeContext’

'No'

Initialize all DFF, RFB and RAM of the chip.

It increases the bitstream size.

'IgnoreRAMFlashClear'

'No'

Do not output error when recognizing a RAM with flash clear.

'ManageAsynchronousReadPort'

'No'

If 'Yes', detect asynchronous read port in memories and repair it in synchronous read port. The read port receive the reversed write clock. It can slow down the design and sometimes may cause invalid behavior.

'ManageUnconnectedOutputs'

'Error'

Undriven outputs of HDL modules are treated as ‘Error', 'Ground', 'Power' or 'Preserve’.

Error: Generates an error

Ground: Connect to '0'

Power: Connect to '1'

Preserve: Preserve attribute set to avoid optimization

'ManageUnconnectedSignals'

'Error'

Undriven internal signals of HDL modules are treated as ‘Error', 'Ground', 'Power' or 'Preserve’.

Error: Generates an error

Ground: Connect to '0'

Power: Connect to '1'

Preserve: Preserve attribute set to avoid optimization

'ManageUninitializedLoops'

'No'

Remove reset-less looped DFF causing extra-mapping and 'X' values in simulation (can be 'No', 'Power, ''Ground').

'MappingEffort'

'Low'

Effort for an optimized mapping in terms of primitive instance merging and simplification (can be 'Low', 'Medium' or 'High'):

Low: almost no optimization
Medium: balanced optimizations
High: almost all optimizations

'MaxRegisterCount'

'2500'

Maximum number of registers handled per HDL module (not the whole design) by the synthesizer.

‘OptimizedMux’

‘Yes’

If set to 'Yes', impulse will identify and convert every mux in the corresponding optimized 4-LUT structure.

'PartitioningEffort'

'Medium'

Define the size of the netlist subset which will be further optimized for timing goals achievement (can be 'Low', 'Medium' or 'High') :

Low: small part
Medium: medium part
· High: huge part

Info
Option is activated only if TimingDriven option is enabled.

'PolishingEffort'

'Medium'

It allows to regenerate locally a signal in TILE which in normal way should be provide by an others TILE in order to reduce utilization of routing resources.

Low: deactivate
Medium: can replicate LUT
High: can replicate LUT and DFF

'ReadyOffWithSoftReset'

‘Yes’

Only available for NG-ULTRA variant.

It links the ready falling edge to soft reset enabling during the power off reset sequence.

‘ReplicationApproval’

‘Yes’

Allow replication in a close TILE if not possible in the current TILE.

No: Do not allow replication
Yes: Allow replication

'RoutingEffort'

'Medium'

Routing Optimization level in terms of routing instances (can be 'Low', 'Medium' or 'High'):

Low: no optimization
Medium: balanced optimizations
High: further optimizations but time consuming

‘SaveTiming'

‘No’

Save STA in .nym project files

No: STA is not saved in project files
Yes: STA is saved in project files

‘Seed’

‘1789’

Seed for placing algorithm start. Depending on the seed, instances are created in a different order and placed so.

Can be used in order to generate several Place & Route with the same synthesized project.

'SetRunAfterContext'

‘No’

Indicate the sequence in the bitstream between run (routing instances enable) and context (initialization values for DFF, RFB, RAM).

No: Run is set before Context
Yes: Run is set after Context

'SharingEffort'

'Medium'

Enables the insertion in lowskew network signal with fanout above the SharingFanout threshold.

Low: Lowskew insertion disabled
Medium/High: Lowskew insertion enabled

Medium and High have the same impact.

'SharingFanout'

'100'

Fanout threshold to insert signal in lowskew network.

This option has an impact only if SharingEffort is set to Medium or High.

‘SimplifyRegions’

‘Yes’

Clear module and region database:

delete modules without instance
delete regions without module
merge identical regions

‘SytemOutputDriven’

'No'

Increase placing close to the ring for instances communicating with.

No: No priority for these instances in algorithm
Yes: Allow priority for these instances in alogrithm

'TimingEffort'

‘High’

Indicates level of iterations for TimingDriven algorithm.

Low: no iteration
Medium: a few iteration
High: more iterations

Info
Option is activated only if TimingDriven option is enabled.

Note
For heavy designs, runtime can increase drastically depending on number of iterations.

'UnusedPads'

'Floating'

State in which the pads must be set when not used. Values can be 'Floating','WeakPullUp', 'WeakPullDown'. Note that when the state is different from 'floating', all the pads are serialized in the bitstream.

Note that ‘WeakPulldown’ value is not available on NX1H35S component.

‘VariantAwareSynthesis’

‘Yes’

If set to ‘Yes’ synthesis will automatically map to equivalent resource when specific resource is depleted. For example using DSP when there are no more CY available (can be ‘Yes’ or ‘No’).

...

Code Block

language	py

project.setOption('MappingEffort', 'Medium')

setOptions(options)

This method allows user to set the values of several nxpython options. The options can be set at any time of the design flow.

...

Code Block

language	py

options = {
	'MappingEffort': 'Medium',
	'AdderToDSPMapThreshold': '12'
}
project.setOptions(options)

setOutputDelay(clock, clock_mode, minimum_delay, maximum_delay, port_list)

This method specifies the data arrival times at the specified output ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

...

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setOutputDelay(getClock('CLK'), 'rise', 1000, 1500, getPorts('dataout[`[0−5]`]'))

setSite(instancePattern, siteName)

This method is used to place a set of register/LUT/Carry instances into a specific TILE site.

...

Code Block
p.setSite('i_cpt_0\|s_cpt_out_reg[0]','TILE[2x2]')#DFF p.setSite('i_cpt_1\|LessThan_L23/lut_0','TILE[5x2]')#LUT LESS_THAN p.setSite('i_cpt_2\|add_L24_stage1','TILE[7x2]')#CY ADD

setTopCellName([library], name)

This method is used to set the name of the HDL top module. If the HDL module is defined inside a library, the name of the library can be passed as the first argument.

...

Note
The name of the HDL top module library are case sensitive.

setVariantName(variant)

This method is used to set the variant of the project. The default value of the variant is 'NG-MEDIUM'.

...

Code Block
project = createProject() project.setVariantName('NG−MEDIUM') project.setVariantName('NG−LARGE') project.setVariantName('NG−ULTRA')

Anchor
synthesizef
synthesizef
synthesize()

This method is used to synthesize the HDL source files and realize the technology mapping against nxpython library.

...

Code Block
project = createProject() project.load('native.nym') project.synthesize()

translateAperture(regionName,horizontal,vertical)

This method is used to move the aperture of a region or of the whole design.

...

Code Block
project = createProject() project.translateAperture('SUB_REGION_0',1,2) project.translateAperture(3,4)

Simulation related methods

This section presents the methods of the simulator object. This object controls the simulation of the design.

addTestBench([library], testBench)

This method is used to add a testBench file. The file can be added to a specific library by passing its name as the first optional argument 'library'. The default library is 'work'.

...

Code Block

language	py

simulator.addTestBench(‘testbench.vhd’)
or
simulator.addTestBench(‘myLib’, ‘testbench.vhd’)

addTestBenchs([library], fileList)

This method is used to add several testbench files. The files can be added to a specific library by passing its name as the first optional argument library. The default library is work.

...

Code Block

language	py

simulator.addTestBenchs([‘testbench1.vhd’, ‘testbench2.vhd’])
or
simulator.addTestBenchs(‘myLib’, [‘testbench1.vhd’, ‘testbench2.vhd’])

addWave(wave)

This method is used to add a signal which will be displayed in vsim. It is also possible to add all the available waves by passing '*' as argument.

...

Code Block

language	py

simulator.addWave(‘*’)
or
simulator.addWave(‘A’)

addWaves(wavelist)

This method is used to add several signals which will be displayed in vsim.

...

Code Block

language	py

simulator.addWaves([‘A’, ‘B’, ‘O’])

destroy()

This method is used to destroy the simulator object.

...

Code Block

language	py

simulator.destroy()

launch(graphical)

This method is used to run the simulation.

...

Code Block

language	py

project = createProject()
project.load(‘routed.nym’)
simulator = project.createSimulator()
simulator.setTestBenchTop(‘testbench’)
simulator.addTestBench(‘testbench.vhd’)
simulator.launch(True)

setDuration(duration)

This method is used to set length in time of the simulation. If not specified (or set to ‘’), vsim will be launched with run -all.

...

Code Block

language	py

simulator.setDuration(‘250ns’)

setTestBenchTop(testBenchTop)

This method is used to set the top cell name of the testbench.

...

Code Block

language	py

simulator.setTestBenchTop(‘testbench’)

setWorkingDirectory(workingDirectory)

This method is used to set the working directory of the simulation

...

Code Block

language	py

simulator.setWorkingDirectory(‘simulation’)

Argument related methods

getClock(clock_name)

This argument method is used to get the clock from a given clock name. A valid clock should be a clock created by command createClock.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'), getClock('clk2'), 'exclusive')

getClockNet(clock_net_name)

This argument method is used to get the net from a given clock net name. It is used by createClock method to specify a clock related point as argument.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)

getClocks(clock_name_expression)

This argument method is used to get the clocks from a given clock name expression. A valid clock should be a clock created by command createClock.

...

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.createClock(getClockNet('CLOCK[3]'), 'test_clkA', 5000, 0, 2000)
project.createClock(getClockNet('CLOCK[4]'), 'test_clkB', 5000, 0, 2000)
project.setClockGroup(getClocks('clk*'), getClocks('test_clk*'), 'exclusive')
project.setClockGroup(getClocks('clk[1-2]'), getClocks('test_clk`[AB]`'), 'exclusive')

getInstances(intance_name)

This argument method is used to get the instances from an instance name. It can be used by some nxpython methods (addMappingDirective, addMemoryInitialization).

...

The list of all the instances identified by impulse from your design is available in the log file operators.rpt in logs directory.

It is also possible to get the list of all the instances identified by impulse using “*” expression as instance name in getInstances method, as following:

project.addMappingDirective(getInstances('*'), 'RAM', 'RAM')

This way, you will see all the available instances in the general.log file in logs directory.

getModels(model_name)

This argument method is used to get the models from a model name. It can be used by some nxpython methods (addMappingDirective, addMemoryInitialization).

...

The list of all the models identified by impulse from your design is available in the log file operators.rpt in logs directory.

It is also possible to get the list of all the models identified by impulse using “*” expression as model name in getModels method, as following:

project.addMappingDirective(getModels('*'), 'RAM', 'RAM')

This way, you will see all the available models in the general.log file in logs directory.

getPort(port_name)

This argument method is used to get the port from a given port name. Some nxpython methods need a port as argument.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500, getPort('RST'))

getPorts(port_name_expression)

This argument method is used to get the ports from a given port name expression. Some nxpython methods need a list of ports as argument.

...

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setOutputDelay(getClock('CLK'), 'rise', 1000, 1500, getPorts('dataout[`[0−5]`]'))

getRegister(register_name)

This argument method is used to get the register from a given register name. Some nxpython methods need a register as argument.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
		              getRegister('UUT2|dout_reg[61]'))

getRegisterClock(register_name)

This argument method is used to get the register clock from a given register name. Some nxpython methods need a clock as argument.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getRegisterClock('reg1'), 'clk', 10000)

getRegisters(register_name_expression)

This argument method is used to get the registers from a given register name expression. Some nxpython methods need a list of registers as argument.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegisters('UUT1|Gen_seq[3].seq_i|temp_reg[`[0-9]`]'),
		               getRegister('UUT2|dout_reg[61]'))

getRegistersByClock(clock_name)

This argument method is used to get all the registers from the same clock domain. Clock must be created before.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('clk1'),'clk1',20000,0,15000)
project.addFalsePath(getRegistersByClock('clk1'), getRegister('UUT2|dout_reg[61]'))

getWFGOutput(wfg_name)

This argument method is used to get the wfg clock from a given wfg name. Some nxpython methods need a clock as argument.

...

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'), getRegister('data_reg[0]'), 'clk1_div2', 				                 
                             {'DivideBy': 2})

Full script example:

This chapter presents the full Python script of the provided VHDL 'simple' example.

...

Code Block

breakoutMode	wide
language	py

import os
import sys
from nxpython import *

dir = os.path.dirname(os.path.realpath(__file__))
project = createProject(dir)
project.setVariantName('NG-MEDIUM')
project.setTopCellName('WOB_MAC_FIR')

project.addFiles([
   'src/src_WOBUL/SUB_ADD.vhd', 
   'src/src_WOBUL/SIN_TAB_8K.vhd', 
   'src/src_WOBUL/SIN_TAB_8K_360.vhd', 
   'src/src_WOBUL/WOBUL.vhd', 
   ])

project.addFiles([
   'src/src_MAC_FIR/MULTI_MAC_FIR_Package.vhd', 
   'src/src_MAC_FIR/CLKGEN.vhd', 
   'src/src_MAC_FIR/SRL_MEM_SYMMETRY_EVEN.vhd', 
   'src/src_MAC_FIR/SRL_MEM_SYMMETRY_ODD.vhd', 
   'src/src_MAC_FIR/TOP_SRL_MEM_MULTI_SYMMETRY.vhd', 
   'src/src_MAC_FIR/MAC_CAPT.vhd', 
   'src/src_MAC_FIR/ADDER_TREE.vhd', 
   'src/src_MAC_FIR/TOP_MAC_FIR.vhd', 
   ])

project.setOptions({
   'MappingEffort': 'High', #can be replaced by  'Medium' or  'Low'
   })

ioBanks = { 
   'IOB12'  : {'voltage': '2.5'},
   'IOB10'  : {'voltage': '1.8'},
   'IOB01'  : {'voltage': '2.5'},
   'IOB00'  : {'voltage': '2.5'},
     }

pads = {
      'CLK25M_IN'  : {'location': 'IOB12_D09P', 'standard': 'LVCMOS', 'drive' :'4mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'RST_PIN'    : {'location': 'IOB10_D12N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},          
      'TRIG_IMMEDIATE_EXT'  : {'location': 'IOB10_D07N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1}, 

      'LEDS_N_8'       : {'location': 'IOB01_D02N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[2]'  : {'location': 'IOB01_D06P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[1]'  : {'location': 'IOB01_D06N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_7_5[0]'  : {'location': 'IOB01_D05P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},

      'LEDS_N_4'  : {'location': 'IOB01_D05N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_3'  : {'location': 'IOB00_D03P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_2'  : {'location': 'IOB00_D03N', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
      'LEDS_N_1'  : {'location': 'IOB00_D01P', 'standard': 'LVCMOS', 'drive' :'8mA', 'registered': '', 'weakTermination': 'None', 'slewRate': 'Medium', 'differential': False, 'terminationReference': 'floating', 'inputSignalSlope': 1},
   }
project.addPads(pads)

#clock constraint
project.createClock(getClockNet('CLK25M_IN'), 'CLK25M_IN', 40000, 0, 20000)

#Create regions ton confine logic
project.addModule('*WOBUL', 'WOBU', 'WOBU-%')
project.createRegion('WOBUR', 1, 2,  2, 4, False)
project.confineModule('WOBU-1', 'WOBUR')

project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[[1-8]].OTHE.OTH_EVEN', 'OTH_EVEN-%')
project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[0].FIRST.FIRST_EVEN', 'FIRST_EVEN-%')
project.addModule('SRL_MEM_SYMMETRY_EVEN', 'FIR_MF|MEM.EVEN.MLT.NR[9].CENT.CENTER_EVEN', 'CENTER_EVEN-%')

project.createRegion('OTH_EV_1_R', 2, 10, 2, 10, False)
project.confineModule('OTH_EVEN-1', 'OTH_EV_1_R')
project.createRegion('OTH_EV_2_R', 3, 10, 3, 10, False)
project.confineModule('OTH_EVEN-2', 'OTH_EV_2_R')
project.createRegion('OTH_EV_3_R', 4, 10, 4, 10, False)
project.confineModule('OTH_EVEN-3', 'OTH_EV_3_R')
project.createRegion('OTH_EV_4_R', 5, 10, 5, 10, False)
project.confineModule('OTH_EVEN-4', 'OTH_EV_4_R')

project.createRegion('OTH_EV_5_R', 6, 10, 6, 10, False)
project.confineModule('OTH_EVEN-5', 'OTH_EV_5_R')
project.createRegion('OTH_EV_6_R', 7, 10, 7, 10, False)
project.confineModule('OTH_EVEN-6', 'OTH_EV_6_R')
project.createRegion('OTH_EV_7_R', 8, 10, 8, 10, False)
project.confineModule('OTH_EVEN-7', 'OTH_EV_7_R')
project.createRegion('OTH_EV_8_R', 9, 10, 9, 10, False)
project.confineModule('OTH_EVEN-8', 'OTH_EV_8_R')
project.createRegion('FIRST_EV_1_R', 1, 10, 1, 10, False)
project.confineModule('FIRST_EVEN-1', 'FIRST_EV_1_R')
project.createRegion('CENT_EV_R', 10, 10, 10, 10, False)
project.confineModule('CENTER_EVEN-1', 'CENT_EV_R')

# Synth                 FIR_MF_GEN_DSP_0_DSP_G_INST_DSP_DSP_INST
# Routed              FIR_MF_GEN_DSP_0_DSP_G_INST_DSP_DSP_INST
# Impulse GUI      FIR_MF|GEN_DSP_0_DSP|G_INST.DSP|DSP_INST
project.addDSPLocation('FIR_MF|GEN_DSP[0].DSP|G_INST.DSP|DSP_INST', 'CGB[1x8]:L') 
project.addDSPLocation('FIR_MF|GEN_DSP[1].DSP|G_INST.DSP|DSP_INST', 'CGB[1x8]:R') 
project.addDSPLocation('FIR_MF|GEN_DSP[2].DSP|G_INST.DSP|DSP_INST', 'CGB[2x8]:L') 
project.addDSPLocation('FIR_MF|GEN_DSP[3].DSP|G_INST.DSP|DSP_INST', 'CGB[2x8]:R') 

# i_WOB_TABLE_ROM_TAB_SINUS_ram0_0_0_0
#project.addRAMLocation('*SINUS*', 'CGB[3x8]')
project.addRAMLocation('WOBU|TABLE|ROM_TAB|SINUS|ram0_0_0_0', 'CGB[1x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_0_0', 'CGB[2x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_1_0', 'CGB[3x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_2_0', 'CGB[4x4]') 
project.addRAMLocation('GEN_SCOP.SCOP|MEASUR|GEN_PRE_TRG*MEM|ram0_0_3_0', 'CGB[5x4]') 

#false paths declarations
#project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[*'), getRegisters('FIR_MF|SUM|PRESUM_reg[*'))
#project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][*'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][0]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][1]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][2]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][2]'))
project.addFalsePath(getRegisters('FIR_MF|GEN_DSP[1].DSP|MAC_OUT_reg[1]'), getRegisters('FIR_MF|SUM|PRESUM_reg[0][4]'))

project.save('native.nym')               
                                         
if not project.synthesize():             
    sys.exit(1)                                                               
project.save('WMFS_Cores_synth.vhd')        
            
if not project.place():                  
    sys.exit(1)                          
project.save('WMFS_Cores_placed.nym')                                         

if not project.route():                  
    sys.exit(1)                          
                                         
project.reportPorts()                    
project.reportInstances()                
                                                                                     
project.save('WMFS_Cores_routed.nym')
project.save('WMFS_Cores_routed.vhd')

analyzer = project.createAnalyzer()
analyzer.launch({
   'conditions': 'worstcase',           # 'typical', 'worstcase', or 'bestcase'
#   'maximumSlack': 10000,
   'searchPathsLimit': 100
   }) 

#bitstream generation
project.generateBitstream('WMFS_Cores.nxb')

print( 'Errors: ', getErrorCount())
print( 'Warnings: ', getWarningCount())

Timing Analysis

Timing path

Timing path is the connection between two certain nodes in the design i.e. connection between primary input and output ports, connection between primary input ports/clock pins and data input pins of the sequential elements, and connection between intermediate clock pins and primary output ports.

Data delay

In impulse, data delay is the delay of a timing path. For example, the delay between the launch edge of the clock at the source register and data input pin of the destination register. In following picture, the path for the data delay between source register DFF1 and destination register DFF2 is shown in blue.

Anchor

	Figure11
	Figure11

...

Clock skew

Clock skew is the difference between the latch clock delay at the destination register and launch clock delay at the source register. Considering the example shown in previous figure, clock skew is calculated as follows:

Code Block
clock skew = Clock delay at DFF2 − Clock delay at DFF1

Setup/Hold time

Setup time is the minimum amount of time required for a signal to be held stable before the clock transition.

Hold time is the minimum amount of time required for a signal to retain its value after the clock transition. In impulse, the analysis of setup/hold time is performed in order to calculate the data arrival time which will be explained shortly.

Recovery/Removal time

Recovery time is the minimum amount of time required for an asynchronous control signal to be held stable after its de-assertion before the next active clock edge. The recovery time calculation corresponds to the setup time calculation but for the asynchronous control signals i.e. reset.

...

Similarly, removal time is the minimum amount of time for an asynchronous signal to be held stable before its de-assertion after the previous active clock edge. The removal time calculation corresponds to the hold time calculation but for the asynchronous signals.

Timing domain

In impulse, the term ‘domain’ is used to define a group of certain timing paths. As mentioned earlier, the timing paths include the connection between primary input and output ports, connection between primary input ports/clock pins and data input pins of the sequential elements, and connection between intermediate clock pins and primary output ports.

...

For example in following figure, three domains D1, D2 and D3 are shown between input and clock "clk" (D1: input to clk), between clock "clk" of source registers and clock "clk" of destination registers (D2: clk to clk), and between clock "clk" and output (D3: clk to output) respectively.

Anchor

	Figure12
	Figure12

...

Data arrival time

In impulse, data arrival time includes the overall data delay, clock skew and setup/hold time (recovery/removal) for a critical timing path in a domain. Based on the setup/hold verification, data arrival time can be either maximum or minimum. In both cases, data arrival time is calculated as follows:

Code Block

breakoutMode	wide

Maximum data arrival time =
       max{∀(path delay = data delay − clock skew + setup or recovery) : path ∈ domain}
Minimum data arrival time =
       min{∀(path delay = data delay − clock skew − hold or removal) : path ∈ domain}

Setup/Recovery, Hold/Removal time relationship

The transfer of data signal from one sequential element to another requires certain timing checks for correct functionality. It involves hold and setup time verification with respect to launch and latch edge of the clock at the source and destination sequential element respectively.

...

Between launch and latch clock, hold and setup time relationship is established which it is essentially the delay between the active edges of these clocks. This relationship is then used to determine positive or negative slack, validating the timing characteristics of the paths in the domain. Following are all the four cases of the active launch and latch clock edges.

Case 1

If both launch and latch clocks have active high edge, hold relationship is established between the current launch edge and the previous or current latch edge ensuring that the data is not captured by the latch edge coming before the launch edge. Similarly, setup relationship is established between the launch edge and the next latch edge ensuring that the data is captured by the latch edge coming after the launch edge.

...

Inthe following figure, hold and setup relationship is shown between a launch and latch clock with no skew. In case of having different frequencies for launch and latch clock, hold relationship is established between the active launch and latch edges with the minimum difference. Thus, hold relationship gives the minimum delay allowed between launch and latch edges. Whereas, the setup relationship is established between launch and latch edges with minimum difference, hence giving the maximum allowed delay between launch and latch edges.

Anchor

	Figure13
	Figure13

...

Case 2

If launch and latch clocks have active high and active low edges respectively, in this case hold relationship is established between active high launch edge and the previous active low latch edge with the minimum difference. Similarly, setup relationship is established between launch edge and the next latch edge with the minimum difference.

...

The following figure shows hold and setup relationship between active high launch clock and active low latch clock.

Anchor

	Figure14
	Figure14

...

Case 3

For the active low launch clock and active high latch clock, the hold relationship gives the minimum delay between active low launch edge and previous active high latch edge. Similarly, setup relationship gives the minimum delay between the active low launch edge and the very next active high latch edge as shown in the following figure.

Anchor

	Figure15
	Figure15

...

Case 4

If both launch and latch clocks have active low edges, the hold relationship is established between active low launch edge and previous active low latch edge. Similarly, setup relationship is established between the active low launch edge and the very next active low latch edge as shown in the following figure.

Anchor

	Figure16
	Figure16

...

Slack calculation

In impulse, setup/recovery slack corresponds to the difference between maximum setup/recovery relationship and maximum data arrival time whereas hold/removal slack corresponds to the difference between minimum data arrival and minimum hold/removal relationship.

Code Block

breakoutMode	wide

Setup/Recovery slack = Maximum setup/recovery relationship − Maximum data arrival time
Hold/Removal slack    = Minimum data arrival time − Minimum hold/removal relationship

Anchor
timingreports
timingreports
Timing reports

In impulse and nxpython, timing analyzer generates a set of reports presenting respectively the summary of analysis, critical paths of each domain, and violation information. All the timing reports are automatically saved in files (.timing) in ‘logs’ directory after a successful analyzing of the routed design.

STA summary

The file "Summary.timing" contains the report of the timing domains as well as hold/removal and setup/recovery summaries in the design. Such domains are grouped by categories:

...

a summary of the presenting domain (similar to Summary.timing);
two lists of critical longest paths and shortest paths;
detailed tables of each found path.

Critical paths table

The critical paths tables show the lists of longest paths and shortest paths for the given timing domain of the design. The details of such critical paths include:

...

Anchor

	Figure18
	Figure18

...

Anchor

	Figure19
	Figure19

...

Path detail

Following the critical paths table, all the listed critical paths are reported in detail. For each part of the path, the table contents the following information: source (beginning of the path), target (ending of the path), routing delay, internal delay, cumulated delay (from the source of the path), setup/recovery time (for data path), hold/removal time (for data path), clock skew (for data path).

Anchor

	Figure20
	Figure20

...

Revision history

The following table shows the revision history of the Impulse_NXpython specification document:

...

Page Comparison

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Table of

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Copyright Notice

Introduction

Package

Description

Installation

Run

NXPython

Anchornxpythonspecnxpythonspec

NXPython Specification

Command

List and

Context

General commands

createProject([workingDirectory])

getErrorCount()

getRemarkCount()

getWarningCount()

listOptions()

printError(message)

printRemark(message)

printText([message])

printWarning(message)

setCoreCount(core_count)

setDirAutoChange(change_project_dir)

change_project_dir

setLogDirectory(log_directory)

log_directory

usage()

version()

Expected expressions for NXpython methods

Impacted methods:

Maintainability:

User use:

Project related methods

addBank(name, dict)

addBanks(dict)

addBlackBox(name, type, mapping, interface)

addBlackBox() : for Preplaced IP

addDSPLocation(pattern, place)

addFalsePath(from_list, to_list)

addFile([library], file)

addFiles([library], fileList)

addHSSLLocation(pattern,location)

addMappingDirective(name, type, mapping)

addMaxDelayPath(from_list, to_list, delay)

addMemoryInitialization(name, type, file)

addMinDelayPath(from_list, to_list, delay)

AnchoraddmoduleaddmoduleaddModule(model, instance, format)

addMulticyclePath(from_list, to_list, cycle_count)

AnchoraddpadaddpadaddPad(name, parameters)

addPads(pads)

addPin(name, location)

addPins(pins)

AnchoraddparamaddparamaddParameter(name, value)

AnchoraddparametersaddparametersaddParameters(parameters)

addPLLLocation(pattern, location)

addRAMLocation(pattern, place)

addRingLocation(name, location)

addRingLocations(dictionary)

addVerilogIncludeDirectory(directory)

addVerilogIncludeDirectories(directoryList)

addVlogDefine(name,value)

addVlogDefines(dictionnary)

addWFGLocation(name, location)

adjustAperture(regionName, above, left, right, below)

applySdcFile(filePath)

clearBanks()

clearFabricPrePlaceConstraints(regionName)

clearPLLs()

clearPads()

clearPins()

clearWFGs()

AnchorconfinemoduleconfinemoduleconfineModule(name, region)

Anchor
nxpythonspec
nxpythonspec

Anchor
addmodule
addmodule
addModule(model, instance, format)

Anchor
addpad
addpad
addPad(name, parameters)

Anchor
addparam
addparam
addParameter(name, value)

Anchor
addparameters
addparameters
addParameters(parameters)

Anchor
confinemodule
confinemodule
confineModule(name, region)

Anchor
createregion
createregion
createRegion(name, column1, row1, column2, row2, exclusive)

Anchor
generatebitstream
generatebitstream
generateBitstream(file)

Anchor
reportinstances
reportinstances
reportInstances()

Anchor
reportports
reportports
reportPorts()

Anchor
reportregions
reportregions
reportRegions()

Anchor
route
route
route()

Anchor
savefile
savefile
save(file,conditions)

Anchor
setaperture
setaperture
setAperture(column1, row1, column2, row2)

Anchor
setfocus
setfocus
setFocus(column, row)

Anchor
setoption
setoption
setOption(name, value)

Anchor
synthesizef
synthesizef
synthesize()