Table of Content

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signal RESET_DELAY : std_logic_vector(7 downto 0);

signal INTERNAL_RESET : std_logic;

begin

process(CLK_generated_by_PLL_and_WFG)  begin

	if rising_edge(CLK_generated_by_PLL_and WFG)  then

		RESET_DELAY <= RESET_DELAY(6 downto 10) & not(RDY);

end if;

end process;

INTERNAL_RESET <= RESET_DELAY(7);

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All the 374 die user’s IOs are available

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Only 192 of the 374 die user’s IOs are available

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The following table summarizes the main IOs features available into complex and simple IO banks.

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Simple banks: Electrical standards and supported electrical parameters

Complex banks: Electrical standards and supported electrical parameters on:

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See the next table for VTO recommended voltage values :

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• For SSTL_2.5V, SSTL_1.8V and HSTL_1.8V, VDDIO 2.5 V and/or 1.8 V, on-chip termination can be activated for all pads in a given bank.

• In the case of SSTL_2.5V (VDDIO 2.5 V), on-chip termination can be activated on maximum 11 pads due to the limitation on VTO power supply rails.

• The value of the input impedance adaptation resistors can be adjusted in the “nxpython” script file by assigning an integer 0 to 15 value for the “termination” parameter (see the figure 12 for the required value), or it can be specified with a value on Ohms. See the NanoXplore “nxmap” Python API documentation for syntax details.

• The graphs on figure 12 show the expected resistor values in function of the parameters assignments versus VDDIO.

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• DCK : delay registers clock (can be asynchronous with SCK/FCK). Usually 2 to 20 MHz. Write operations occur on DCK rising edge.

• DID(4:0) : address identifier of the considered I/O in the complex bank (0 to 29).

• DRA(4:0) : address of the I/O in the considered complex bank (0 to 29). Note that when DRA = DID, the DRO outputs, as well as FLD and FLG flags outputs of the considered I/O go to low impedance (allowing thus to be read by the fabric).

• DS(1:0) : allow to select the destination register into the DRA selected I/O. See next table for details.

• DRI(5:0) :value to be written into the selected register.

• DRL : active high load (write enable)

• DIG : active low multicast write. Must remain high for register by register access, and corresponding FLD / FLG activation.

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Here is a summary of the NX_RAM main features and possible configurations.

The next figure shows a simplified internal diagram of a RAM block.

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The blue highlighted configurations are directly supported by “nxmap”, just by assigning a generic parameter when instantiating the NX_RAM primitive. However, the user can define any of the following block RAM configurations by instantiating the NX_RAM primitive, and properly assigning all related generic parameters. (See Library_Guide.pdf for more details).

Data input pins and RAM block configuration:

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“A” input is 24-bit wide. An input multiplexer allows to select the 24 bits coming from the fabric or 18 bits from the “CAO” output of the previous (left) DSP block. “A” can go to one of the multiplier inputs through 0, 1, 2 or 3 pipeline registers, and/or forward its 18 LSBs to the “CAI” input of the neighboring (right) DSP block by using its CAO cascade output.

“A” input is most often used as an input to the multiplier.

“CAI” input: 18-bit input that can be used when the “A” input must receive the signal from the previous (on the right) DSP block via its “COA” chaining connection (direct routing, 0 ns delay), instead of the fabric.

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“B” input is 18-bit wide. An input multiplexer allows to select the 18-bit signal coming from the fabric or the18 bits from the “CBO” output of the previous (left) DSP block. “B” can be directed to one of the pre-adder/subtracter, and/or to one of the multiplier inputs through 0, 1, 2 or 3 pipeline registers, and/or forward its 18 to the “CBI” input of the neighboring (right) DSP block by using its CBO cascade output.

“B” input is often used as a second input to the multiplier. It can also be used as operand of the pre-adder/subtracter.

• “CBI” input: 18-bit input that can be used when the “B” input must receive the signal from the previous (left) DSP block via its “COB” chaining connection (direct routing, 0 ns delay), instead of the fabric.

• “C” input is 36-bit wide. It’s directed to the ALU as a second operand (if required). “C” input can use 0 or 1 level of pipeline.

“C” input is often used as constant value input required for rounding operation.

“D” input is 18-bit wide. It’s directed to the pre-adder/subtracter through 0 or 1 level of pipeline registers.

“D” input is often used as input of the pre-adder/subracter. However for ALU dynamic opcode, the bits D(5:0) are used to dynamically select the operation to be performed.

“CZI” input is 56-bit wide. It comes from the neighboring (left) DSP block. It’s directed to the ALU (usually configured as post-adder/subtractor) through 0 or 1 level of pipeline registers.

“CZI” input is used when various DSP blocks have to be chained, for example in FIR filters and other DSP functions implementation.

Main DSP block outputs:

“CAO” is 18-bit wide. It’s used to forward the “A” input to the next (right) DSP block through 0, 1, 2, or 3 level of pipeline registers.

“CAO” input is used when two or mode DSP blocks have to be chained to forward data.

“CBO” is 18-bit wide. It’s used to forward the “B” input to the next (right) DSP block through 0, 1, 2, or 3 level of pipeline registers.

“COB” input is used when two or mode DSP blocks have to be chained to forward data.

• “Z” output is 56-bit wide. It’s the main DSP block output to the fabric via general routing. It can be registered or not. The value available at the “Z” output is feedback to the ALU via the X-MUX (for example to implement an accumulator).

• “CZO” output is also 56-bit wide. It allows to forward the registered or un-registered ALU output to the next (right) DSP block, via direct routing (no delay).

“CZO” is particularly useful to chain DSP blocks for FIR filters and other DSP functions requiring more than one DSP block.

DSP block features and operators:

...

All the 374 die user’s IOs are available

...

Only 192 of the 374 die user’s IOs are available

...

The following table summarizes the main IOs features available into complex and simple IO banks.

...

Simple banks: Electrical standards and supported electrical parameters

Complex banks: Electrical standards and supported electrical parameters on:

...

See the next table for VTO recommended voltage values :

...

• For SSTL_2.5V, SSTL_1.8V and HSTL_1.8V, VDDIO 2.5 V and/or 1.8 V, on-chip termination can be activated for all pads in a given bank.

• In the case of SSTL_2.5V (VDDIO 2.5 V), on-chip termination can be activated on maximum 11 pads due to the limitation on VTO power supply rails.

• The value of the input impedance adaptation resistors can be adjusted in the “nxpython” script file by assigning an integer 0 to 15 value for the “termination” parameter (see the figure 12 for the required value), or it can be specified with a value on Ohms. See the NanoXplore “nxmap” Python API documentation for syntax details.

• The graphs on figure 12 show the expected resistor values in function of the parameters assignments versus VDDIO.

...

...

• DCK : delay registers clock (can be asynchronous with SCK/FCK). Usually 2 to 20 MHz. Write operations occur on DCK rising edge.

• DID(4:0) : address identifier of the considered I/O in the complex bank (0 to 29).

• DRA(4:0) : address of the I/O in the considered complex bank (0 to 29). Note that when DRA = DID, the DRO outputs, as well as FLD and FLG flags outputs of the considered I/O go to low impedance (allowing thus to be read by the fabric).

• DS(1:0) : allow to select the destination register into the DRA selected I/O. See next table for details.

• DRI(5:0) :value to be written into the selected register.

• DRL : active high load (write enable)

• DIG : active low multicast write. Must remain high for register by register access, and corresponding FLD / FLG activation.

...

Here is a summary of the NX_RAM main features and possible configurations.

The next figure shows a simplified internal diagram of a RAM block.

...

The blue highlighted configurations are directly supported by “nxmap”, just by assigning a generic parameter when instantiating the NX_RAM primitive. However, the user can define any of the following block RAM configurations by instantiating the NX_RAM primitive, and properly assigning all related generic parameters. (See Library_Guide.pdf for more details).

Data input pins and RAM block configuration:

...

“A” input is 24-bit wide. An input multiplexer allows to select the 24 bits coming from the fabric or 18 bits from the “CAO” output of the previous (left) DSP block. “A” can go to one of the multiplier inputs through 0, 1, 2 or 3 pipeline registers, and/or forward its 18 LSBs to the “CAI” input of the neighboring (right) DSP block by using its CAO cascade output.

“A” input is most often used as an input to the multiplier.

“CAI” input: 18-bit input that can be used when the “A” input must receive the signal from the previous (on the right) DSP block via its “COA” chaining connection (direct routing, 0 ns delay), instead of the fabric.

...

“B” input is 18-bit wide. An input multiplexer allows to select the 18-bit signal coming from the fabric or the18 bits from the “CBO” output of the previous (left) DSP block. “B” can be directed to one of the pre-adder/subtracter, and/or to one of the multiplier inputs through 0, 1, 2 or 3 pipeline registers, and/or forward its 18 to the “CBI” input of the neighboring (right) DSP block by using its CBO cascade output.

“B” input is often used as a second input to the multiplier. It can also be used as operand of the pre-adder/subtracter.

• “CBI” input: 18-bit input that can be used when the “B” input must receive the signal from the previous (left) DSP block via its “COB” chaining connection (direct routing, 0 ns delay), instead of the fabric.

• “C” input is 36-bit wide. It’s directed to the ALU as a second operand (if required). “C” input can use 0 or 1 level of pipeline.

“C” input is often used as constant value input required for rounding operation.

“D” input is 18-bit wide. It’s directed to the pre-adder/subtracter through 0 or 1 level of pipeline registers.

“D” input is often used as input of the pre-adder/subracter. However for ALU dynamic opcode, the bits D(5:0) are used to dynamically select the operation to be performed.

“CZI” input is 56-bit wide. It comes from the neighboring (left) DSP block. It’s directed to the ALU (usually configured as post-adder/subtractor) through 0 or 1 level of pipeline registers.

“CZI” input is used when various DSP blocks have to be chained, for example in FIR filters and other DSP functions implementation.

Main DSP block outputs:

“CAO” is 18-bit wide. It’s used to forward the “A” input to the next (right) DSP block through 0, 1, 2, or 3 level of pipeline registers.

“CAO” input is used when two or mode DSP blocks have to be chained to forward data.

“CBO” is 18-bit wide. It’s used to forward the “B” input to the next (right) DSP block through 0, 1, 2, or 3 level of pipeline registers.

“COB” input is used when two or mode DSP blocks have to be chained to forward data.

• “Z” output is 56-bit wide. It’s the main DSP block output to the fabric via general routing. It can be registered or not. The value available at the “Z” output is feedback to the ALU via the X-MUX (for example to implement an accumulator).

• “CZO” output is also 56-bit wide. It allows to forward the registered or un-registered ALU output to the next (right) DSP block, via direct routing (no delay).

“CZO” is particularly useful to chain DSP blocks for FIR filters and other DSP functions requiring more than one DSP block.

DSP block features and operators:

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In all configuration modes, the configuration clock must be provided to the FPGA on the CLK dedicated input pin. Its frequency can range from 20 MHz to 50 MHz, in any case it must be strictly greater than twice the JTAG (TCK) frequency – if used.

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