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Using a low-skew dedicated complex pad (highly recommended)
Using a simple/complex pad and buffer in global_lowskew modeUsing a simple/complex pad and buffer in local_lowskew modeCommon to System Converter (CSC)
Using a simple/complex pad connected to a WFG (not recommended)
Using low-skew dedicated pads reduces clock skew delays in order to reach best performances during Static Timing Analysis.
Global_lowskew mode has to be used in case of registers from different tiles are on low-skew signal destination. Otherwise, if registers are in the same tile, it is enough to use local_lowskew For NG-MEDIUM/NG-LARGE, CSC is instantiated thanks to NX_BD in global_lowskew mode.
For NG-ULTRA, CSC is instantiated thanks to NX_GCK in CSC mode.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_BD NX_GCK NX_WFG |
MethodsaddModule createRegion confineModule |
Table: Design LowskewManagement environment
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NanoXmap check: After project launching, the user can check in progresslowskew.rpt that 2 clock buffers and 2 WFG are counted. Routing ways are observable in the GUI.
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Simulation check: No simulation environment is available for this testcaseand in the GUI that clocks are inserted in the lowskew through multiple ways.
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Simulation check: Clocks go through different ways without impact.
Board check: No board purpose for this testcase.
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Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createRegion modifyRegion addModule confineModule constrainModule removeSoftModules |
Table: PlacingConstraint Region environment
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| Code Block |
|---|
| Summary of DOMAIN_clk_main_to_clk_main
| +---------------------------------------+--------------------------+-------------------------------------------+--------------------------------------------+
| | Domain | Frequency | Hold/Removal Summary | Setup/Recovery Summary |
| +-------------------+-------------------+------------+-------------+---------+--------------+------------------+----------+--------------+------------------+
| | Source | Target | Required | Maximum | Slack | Minimum Data | Minimum Required | Slack | Maximum Data | Maximum Required |
| | | | | | | Arrival Time | Relationship | | Arrival Time | Relationship |
| +-------------------+-------------------+------------+-------------+---------+--------------+------------------+----------+--------------+------------------+
| | clk_main (Rising) | clk_main (Rising) | 25.000 MHz | 368.460 MHz | 1.588ns | 1.588ns | 0ps | 37.286ns | 2.714ns | 40.000ns |
| +-------------------+-------------------+------------+-------------+---------+--------------+------------------+----------+--------------+------------------+
| | Total | 1 |
| +---------------------------------------+-------------------------------------------------------------------------------------------------------------------+
| |
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
SpacewireTiming
Description:
The user must be able to get all needed timing in case of recovery clock like Spacewire one.
Spacewire recovery clock is generated by a XOR between DIN and SIN, data and strobe input signals.
The architecture looks like the following:
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Spacewire clock creation must be done as follows as the tool will separate it in 2 clock signals with one inverted.
| Code Block | ||
|---|---|---|
| ||
p.createClock(target=getRegisterClock('din_r_reg'), name='input_xor_rising', period=10.0, rising=0.0, falling=5.0)
p.createClock(target=getRegisterClock('din_f_reg'), name='input_xor_falling', period=10.0, rising=0.0, falling=5.0) |
However, in order to get timings before the XOR output, STA must be launched without these clock creation constraints.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock |
Table: StaConstraint SpacewireTiming environment
Option: There is one option to check the impact of this constraint:
No option: no clock creation.
CreateClock: Both clocks are created.
NanoXmap check: After project launching, the user can get all needed timing paths in timing log files.
No option: no clock creation.
For Input to DIN:
| Code Block | ||
|---|---|---|
| ||
| Clock network delay to destination register:
| +-----------------------------------------+----------------------------------------+---------------+----------------+-----------------+
| | Source | Target/Net | Routing delay | Internal delay | Cumulated delay |
| +-----------------------------------------+----------------------------------------+---------------+----------------+-----------------+
| | Pin: spw_din.O | Net: spw_din | 7.329ns | - | 7.329ns |
| | Pin: LOGIC|lut_1[D]~csc~lut~exp[6:1].I2 | Pin: LOGIC|lut_1[D]~csc~lut~exp[6:1].O | - | 318ps | 7.647ns |
| | Pin: LOGIC|lut_1[D]~csc~lut~exp[6:1].O | Net: input_xor | 1.078ns | - | 8.725ns |
| +-----------------------------------------+----------------------------------------+---------------+----------------+-----------------+
| | Total | 8.407ns | 318ps | 8.725ns |
| +----------------------------------------------------------------------------------+---------------+----------------+-----------------+ |
CreateClock: Both clocks are created.
For Input to falling edge clock DFF:
| Code Block | ||
|---|---|---|
| ||
| RPath summary:
| +---------+----------------+------------------+------------+-------------------+--------------+--------+--------+
| | Slack | Source | Target | Data Delay | Latch Clock Delay | Hold/Removal | Depth | Note |
| +---------+----------------+------------------+------------+-------------------+--------------+--------+--------+
| | 6.764ns | Pin: spw_din.O | Pin: din_f_reg.I | 7.647ns | 1.167ns | -284ps | 1 | (-R) |
| +---------+----------------+------------------+------------+-------------------+--------------+--------+--------+
|
| Clock network delay to destination register:
| +-------------------------------+------------+---------------+----------------+-----------------+
| | Source | Target/Net | Routing delay | Internal delay | Cumulated delay |
| +-------------------------------+------------+---------------+----------------+-----------------+
| | Pin: LOGIC|lut_0[D]~csc~lut.O | Net: n15 | 1.167ns | - | 1.167ns |
| +-------------------------------+------------+---------------+----------------+-----------------+
| | Total | 1.167ns | 0ps | 1.167ns |
| +--------------------------------------------+---------------+----------------+-----------------+
|
| Data path detail:
| +------------------+-------------------+--------+--------+---------------+----------------+-----------------+--------------+-------------------+
| | Source | Target/Net | Module | Region | Routing delay | Internal delay | Cumulated delay | Hold/Removal | Latch Clock Delay |
| +------------------+-------------------+--------+--------+---------------+----------------+-----------------+--------------+-------------------+
| | Pin: spw_din.O | Net: spw_din | ~ | ~ | 7.647ns | - | 7.647ns | | |
| | Pin: din_f_reg.I | Pin: din_f_reg.CK | ~ | ~ | - | - | 7.647ns | -284ps | |
| +------------------+-------------------+--------+--------+---------------+----------------+-----------------+--------------+-------------------+
| | Total | 7.647ns | 0ps | 7.647ns | | 1.167ns |
| +--------------------------------------------------------+---------------+----------------+-----------------+--------------+-------------------+
| |
For Input to rising edge clock DFF:
| Code Block | ||
|---|---|---|
| ||
| RPath summary:
| +--------+----------------+------------------+------------+-------------------+----------------+--------+--------+
| | Slack | Source | Target | Data Delay | Latch Clock Delay | Setup/Recovery | Depth | Note |
| +--------+----------------+------------------+------------+-------------------+----------------+--------+--------+
| | 0ps | Pin: spw_din.O | Pin: din_r_reg.I | 7.784ns | 1.078ns | 337ps | 1 | (-R) |
| +--------+----------------+------------------+------------+-------------------+----------------+--------+--------+
|
| Clock network delay to destination register:
| +----------------------------------------+----------------+---------------+----------------+-----------------+
| | Source | Target/Net | Routing delay | Internal delay | Cumulated delay |
| +----------------------------------------+----------------+---------------+----------------+-----------------+
| | Pin: LOGIC|lut_1[D]~csc~lut~exp[6:1].O | Net: input_xor | 1.078ns | - | 1.078ns |
| +----------------------------------------+----------------+---------------+----------------+-----------------+
| | Total | 1.078ns | 0ps | 1.078ns |
| +---------------------------------------------------------+---------------+----------------+-----------------+
|
| Data path detail:
| +------------------+-------------------+--------+--------+---------------+----------------+-----------------+----------------+-------------------+
| | Source | Target/Net | Module | Region | Routing delay | Internal delay | Cumulated delay | Setup/Recovery | Latch Clock Delay |
| +------------------+-------------------+--------+--------+---------------+----------------+-----------------+----------------+-------------------+
| | Pin: spw_din.O | Net: spw_din | ~ | ~ | 7.784ns | - | 7.784ns | | |
| | Pin: din_r_reg.I | Pin: din_r_reg.CK | ~ | ~ | - | - | 7.784ns | 337ps | |
| +------------------+-------------------+--------+--------+---------------+----------------+-----------------+----------------+-------------------+
| | Total | 7.784ns | 0ps | 7.784ns | | 1.078ns |
| +--------------------------------------------------------+---------------+----------------+-----------------+----------------+-------------------+ |
Simulation check: No simulation environment is available for this testcase.
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