Copyright
All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without consent of NanoXplore.
Introduction
Aim of document
This document is intended to guide users on Training Package testcases.
In order to be more familiar with the Training Package environment, please refer to TrainingPackage_UserManual. For any kind of help, please contact NanoXplore support team at support@nanoxplore.com.
Content
For each testcase of the Training Package, an application note informing about implemented NanoXplore python methods (cf Impulse User Manual) and NanoXplore primitives (cf https://nanoxplore-wiki.atlassian.net/wiki/spaces/SANDBOX/pages/202244165) is provided in this document.
Test plan
List of categories
Testcases are grouped by category depending on the aim of the testcase (python method, primitive, …).
...
Attribute: Attributes can be inserted in the design in order to add a constraint on a register, a memory, …
Board: Designs to program NanoXplore evaluation boards (DevKit / BringUp).
Component: Multiple configurations for NanoXplore primitives.
Design: Various types of designs without any specific IP.
Init: Memory initialization
Ip: Designs implementing NanoXplore Ips.
MappingDirective:Directive of elements mapping in NanoXplore primitives.
Pad: Pad configurations.
PlacingConstraint: Constraints for manual placing of NanoXplore primitives.
ProcessingSystem: Communication between Programmable Logic and Processing System.
StaConstraint: Constraintsfor static time analysis.
List of testcases
Hereafter the list of all available testcases for each category:
Attribute:
NxInit
NxPort
NxUse
SynKeep
SynPreserve
Board:
Scope
SwichBlink
ThermalSensor
Component
ClockSwitch
Ddfr
DspConfig
IoConfig
PllConfig
RamConfig
RfbConfig
Service
Soc
WfgConfig
Design
DelayIo
DspCascaded
DspMultAcc
DspTranspose
LowskewManagement
MemInfer
Init
Ram
Ip
CrossDomain
Ddr2Dfi
HsslEsistream
R5AxiMaster
R5AxiSlave
R5Jtag
Serdes
SpacewireLoopback
SpacewireRoadmap
SpacewireRx
MappingDirective
Adder
BlackBox
Memory
Pad
Parameter
Registered
PlacingConstraint
Aperture
ConstrainPath
DspLocation
ExportSites
Focus
Obstruction
PreplaceIpPreplaceI
RamLocation
Region
RingLocation
Site
ProcessingSystem
Interruptions
Watchdog
SoC AXI test
StaConstraint
CaseAnalysis
ClockGroup
DelayPath
FalsePath
GeneratedClock
InputOutputDelay
ReportPath
SpacewireTiming
Testcase content
Each testcase of this application note contains the following fields:
Description: Global description of the aim of the testcase highlighting which method, primitive, IP, … is concerned and illustrated.
Environment: It informs about all possibilities that can be performed in that testcase in order to help the user to get examples.
Variant | All compliant variants from NanoXplore chips family |
Embedded | Embedded variant compliance in case the testcase only needs the fabric |
Simulation | Indicates whether a simulation environment is available or not on Modelsim |
Attributes | All attributes implemented in the VHDL code |
IP | All NanoXplore primitives, hard or soft IP implemented in the VHDL code |
Methods | All NanoXplore python methods implemented in the python script |
Table: Testcase example environment
Option: Project can be launched with or without an option when launching the python script in order to stress the difference if option is set or not. Please have a look at the https://nanoxplore-wiki.atlassian.net/wiki/spaces/SANDBOX/pages/202244782 for more information.
NanoXmap check: What the user can observe after launching the NanoXmap project.
Simulation check: What the user can observe after launching the Modelsim simulation in case of available simulation environment.
Board check: What the user can observe after programming the bitstream on an DevKit Evaluation Board.
Testcase Description
Attribute
NxInit
Description:
By using nx_init attribute, the user can initialize an inferred memory directly in the design code. It is an alternative way from using the addMemoryInitialization NXpython method in the python script. The syntax is the following one:
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | Yes |
Attributes | nx_init |
IP |
|
Methods |
|
Table: Attribute NxInit environment
...
Board check: No board purpose for this testcase.
NxPort
Description:
By using nx_port attribute, the user can add parameters to the design top IOs directly in the design code. It is an alternative way from using the addPad NXpython method in the python script. The syntax is the following one:
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes | nx_port |
IP |
|
Methods |
|
Table: Attribute NxPort environment
...
Board check: No board purpose for this testcase.
NxUse
Description:
By using nx_use attribute, the user can add directive for inferred elements directly in the design code. It is an alternative way from using the addMappingDirective NXpython method in the python script. The syntax is the following one:
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes | nx_use |
IP |
|
Methods |
|
Table: Attribute NxUse environment
...
Board check: No board purpose for this testcase.
SynKeep
Description:
By using syn_keep attribute, the user can avoid any optimization of a combinatorial signal directly in the design code. syn_keep attribute can be replaced by syn_noprune attribute with exactly the same impact. The syntax is the following one:
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes | syn_keep syn_noprune |
IP |
|
Methods |
|
Table: Attribute SynKeep environment
...
Board check: No board purpose for this testcase.
SynPreserve
Description:
By using syn_preserve attribute, the user can avoid any optimization of a register signal directly in the design code. The syntax is the following one:
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes | syn_preserve |
IP |
|
Methods |
|
Table: Attribute SynPreserve environment
...
Board check: No board purpose for this testcase.
Board
Scope
Description:
The user can use NxScope IP by implementing it in the design code in order to check signals on a NanoXplore Evaluation board.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NxScope NxScopeV2 |
Methods |
|
Table: Board Scope environment
...
For NG-ULTRA, NxScopeV2 IP Core is used instead of NxScope.
SwitchBlink
Description:
The user can program a NanoXplore Evaluation board (DevKit) with a simple bitstream using switches and LEDs.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | True |
Attributes |
|
IP |
|
Methods |
|
Table: Board SwitchBlink environment
...
-> Make sure all this check points are OK.
ThermalSensor
Description:
The user can interface with the internal thermal sensor in order to retrieve the junction temperature.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM |
Embedded | No |
Simulation | No |
Attributes |
|
IP |
|
Methods | initRegister |
Table: Board ThermalSensor environment
...
Board check: Temperature bus is displayed on LEDs.
Component
ClockSwitch
Description:
The user can gate and mux clocks using NanoXplore macro cells in the design code.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | Yes |
Attributes |
|
IP | NX_CKS NX_GCK |
Methods |
|
Table: Component ClockSwitch environment
...
Board check: No board purpose for this testcase.
Ddfr
Description:
The user can use double data rate input/output using NanoXplore macro cells in the design code.
...
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | Yes |
Attributes |
|
IP | NX_IDDFR NX_ODDFR |
Methods |
|
Table: Component Ddfr environment
...
Board check: No board purpose for this testcase.
DspConfig
Description:
The user can make operations using NanoXplore DSP macro cells in the design code.
Hereafter the list of available configurations:
NAME | Description |
ADD36 | 36 bits adder |
SUB36 | 36 bits subtractor |
SMUL18 | 18 bits signed multiplicator |
UMUL18 | 18 bits unsigned multiplicator |
ADD36_PIPE | 36 bits adder with input/output pipe stages |
SUB36_PIPE | 36 bits subtractor with input/output pipe stages |
SMUL18_PIPE | 18 bits signed multiplicator with input/output pipe stages |
UMUL18_PIPE | 18 bits unsigned multiplicator with input/output pipe stages |
Table: Component DspConfig configuration description
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | Yes |
Simulation | Yes |
Attributes |
|
IP | NX_DSP_WRAP |
Methods |
|
Table: Component DspConfig environment
...
Board check: No board purpose for this testcase.
IoConfig
Description:
The user can make operations using NanoXplore IO macro cells in the design code.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_IOB |
Methods |
|
Table: Component IoConfig environment
...
Board check: No board purpose for this testcase.
PllConfig
Description:
The user can generate clocks using NanoXplore PLL macro cells in the design code.
Hereafter the list of available configurations:
NAME | Description |
DELAY | Feedback clock is delayed |
REF_DIVIDED (MEDIUM) / OSC_REF (LARGE/ULTRA) | Input REF is divided as reference clock / Internal oscillator is used and divided as reference clock |
OUT_DIVIDED | All outputs get a not null divider |
EXT_FBK | Feedback is external |
Table: Component PllConfig configuration description
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | Yes |
Attributes |
|
IP | NX_PLL |
Methods |
|
Table: Component PllConfig environment
...
Board check: No board purpose for this testcase.
RamConfig
Description:
The user can store data using NanoXplore RAM macro cells in the design code.
Hereafter the list of available configurations:
NAME | Description |
NOECC | 2kx24 memory with rising edge clock without ECC |
FAST | 2kx18 memory with rising edge clock with ECC detection only |
SLOW | 2kx18 memory with rising edge clock with ECC read repairing |
NOECC_PIPE | 2kx24 memory with falling edge clock without ECC with input/output pipe stages |
FAST_PIPE | 2kx18 memory with falling edge clock with ECC detection only with input/output pipe stages |
SLOW_PIPE | 2kx18 memory with falling edge clock with ECC read repairing with input/output pipe stages |
Table: Component RamConfig configuration description
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | Yes |
Attributes |
|
IP | NX_RAM_WRAP |
Methods |
|
Table: Component RamConfig environment
...
Board check: No board purpose for this testcase.
RfbConfig
Description:
The user can store data using NanoXplore Register File macro cells in the design code.
Hereafter the list of available configurations for MEDIUM/LARGE:
NAME | Description |
FALLING | Write and Read accesses are falling edge sensitive |
RISING | Write and Read accesses are rising edge sensitive |
Table: Component RfbConfig configuration description MEDIUM/LARGE
Hereafter the list of available configurations for ULTRA:
NAME | Description |
SPRAM | Single port RFB |
FALLING DPRAM | Dual port RFB falling edge sensitive |
RISING DPRAM | Dual port RFB rising edge sensitive |
WIDTH_EXT | 2 RFB are used for twice larger words |
HIGHT_EXT | 2 RFB are used for twice larger number of words |
2R1W | 2 RFB are used for 2 read ports |
RISING_FIFO_WIDTH_EXT | FIFO: 2 RFB are used for twice larger words |
RISING_FIFO_HEIGHT_EXT | FIFO: 2 RFB are used for twice larger number of words |
Table: Component RfbConfig configuration description ULTRA
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | Yes |
Attributes |
|
IP | NX_RFB_WRAP NX_RFBDP_U_WRAP NX_RFBSP_U_WRAP NX_XRFB_32x36 NX_XRFB_64x18 NX_XFIFO_64x18 NX_XFIFO_32x36 |
Methods |
|
Table: Component RamConfig environment
...
Board check: No board purpose for this testcase.
Service
Description:
The user can interface with the Bitstream Manager and the Service bank using NanoXplore Service macro cell in the design code.
...
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | Yes |
Attributes |
|
IP | NX_SERVICE_WRAP |
Methods | createClock |
Table: Component Service environment
...
Board check: No board purpose for this testcase.
Soc
Description:
The user can interface with the Soc using NanoXplore SOC_INTERFACE macro cell in the design code.
...
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_SOC_INTERFACE_WRAP |
Methods |
|
Table: Component Soc environment
...
Board check: No board purpose for this testcase.
WfgConfig
Description:
The user can generate clocks using NanoXplore WFG macro cells in the design code.
Hereafter the list of available configurations:
NAME | Description |
BYPASS | Input is directly routed to the output |
BYPASS_INVERT | Input is inverted to generate output |
DIV2 | Input is divided by 2 with a pattern to generate output with rising edge generation |
DIV2_FALLING | Input is divided by 2 with a pattern to generate output with falling edge generation |
DIV2_DELAY | Input is divided by 2 with a pattern to generate output with an additional delay |
DIV16 | Input is divided by 16 with a pattern to generate output |
DIV40 (ULTRA) | Input is divided by 16 with a divider to generate output |
Table: Component WfgConfig configuration description
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | Yes |
Attributes |
|
IP | NX_WFG |
Methods |
|
Table: Component WfgConfig environment
...
Board check: No board purpose for this testcase.
Design
DelayIo
Description:
The user can drive delays on IO statically or dynamically using NanoXplore macro cells in the design code.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_WFG NX_IOM_CONTROL NX_IOM_DRIVER NX_IOB |
Methods | createClock |
Table: Design DelayIo environment
...
Board check: No board purpose for this testcase.
DspCascaded
Description:
The user can cascade DSP using NanoXplore DSP macro cells in the design code in order to compute large operations.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP | NX_DSP_SPLIT |
Methods |
addDspLocation
Table: Design DspCascaded environment
...
Board check: No board purpose for this testcase.
DspMultAcc
Description:
The user can infer a 12*16+36 operations mapped in DSP.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods |
|
Table: Design DspMultAcc environment
...
Board check: No board purpose for this testcase.
DspTranspose
Description:
The user can implement a 6-tap transpose Finite Impulsion Response filter.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP | NX_TRANSPOSE_FIR |
Methods |
|
Table: Design DspTranspose environment
...
Board check: No board purpose for this testcase.
LowskewManagement
Description:
The user can interface with the low-skew network through several ways.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_BD NX_GCK NX_WFG |
Methods |
Table: Design LowskewManagement environment
...
Board check: No board purpose for this testcase.
MemInfer
Description:
The user can infer memories without instantiating NanoXplore macro cells in the design code.
Hereafter the list of all inferred memories:
NAME | Description |
ROM | Read Only Memory |
SPRAM | Single-Ported Random-Access Memory |
DPRAM | Double-Ported Random-Access Memory |
SPRAM_ECC | Single-Ported Random-Access Memory with Error Code Correction |
DPRAM_ECC | Double-Ported Random-Access Memory with Error Code Correction |
Table: Design MemInfer configuration description
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_ECC |
Methods |
|
Table: Design MemInfer environment
...
Board check: No board purpose for this testcase.
Init
Ram
Description:
The user can initialize a memory using the addMemoryInitialization NXpython method in the python script. The syntax is the following one:
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | Yes |
Attributes |
|
IP |
|
Methods | addMemoryInitialization getInstances |
Table: Init Ram environment
...
Board check: No board purpose for this testcase.
Ip
CrossDomain
Description:
The user can cross clock domain properly thanks to NanoXplore IP. Implemented IP are:
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | Yes |
Attributes |
|
IP | IP_CDC FIFO |
Methods | addIp |
Table: Ip CrossDomain environment
...
Board check: No board purpose for this testcase.
Ddr2Dfi
Description:
The user can interface with a DDR2 memory thanks to the NanoXplore DDR2 DFI IP.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | IP_DFI |
Methods | addIp |
Table: Ip Ddr2Dfi environment
...
Board check: Switches and leds allow to control and receive data.
HsslEsistream
Description:
The user can interface with HSSL links thanks to the NanoXplore HSSL macro cell.
...
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_HSSL_L_FULL |
Methods | addHSSLLocation constrainModule |
Table: Ip HsslEsistream environment
...
ERROR FLAG deactivated on J15 PIN1
HSSL_CLK at 48MHz on J15 PIN3
ESISTREAM SYNC RX/TX activated on J15 PIN 5
RX_PLL_LOCKED activated on J15 PIN7
PMA RX CLOCK on on J15 PIN13
R5AxiMaster
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
...
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_R5_L_WRAP NX_SCOPE NX_PLL NX_WFG |
Methods | addMemoryInitialization addMappingDirective |
Table: Ip R5AxiMaster environment
...
Board check: No board purpose for this testcase.
R5AxiSlave
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
...
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_R5_L_WRAP NX_SCOPE NX_PLL NX_WFG |
Methods | addMemoryInitialization addMappingDirective |
Table: Ip R5AxiSlave environment
...
Board check: No board purpose for this testcase.
R5Jtag
Description:
The user can interface with R5 Core thanks to the NanoXplore R5 interface macro cell.
...
Here after the table of compliances for this testcase.
Variant | NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_R5_L_WRAP |
Methods |
|
Table: Ip R5Jtag environment
...
Board check: No board purpose for this testcase.
Serdes
Description:
The user can send and receive data at high speed thanks to the NanoXplore SERDES macro cells.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_SER NX_DES NX_WFG |
Methods |
|
Table: Ip Serdes environment
...
Board check: No board purpose for this testcase.
SpacewireLoopback
Description:
The user can communicate with Spacewire link thanks to the NanoXplore SpaceWire macro cell.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | IP_SPW_BANK IP_FIFO_part NX_PLL NX_WFG |
Methods | addIp |
Table: Ip SpacewireLoopback environment
...
3- Check data is displayed on LED.
SpacewireRoadmap
Description:
The user can communicate with Spacewire link and Roadmap protocol thanks to the NanoXplore SpaceWire macro cell.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_PLL NX_WFG |
Methods |
|
Table: Ip SpacewireRoadmap environment
...
Board check: No board purpose for this testcase.
SpacewireRx
Description:
The user can retrieve data from a Spacewire Link generating the recovery clock.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | spw_rx |
Methods |
|
Table: Ip SpacewireRx environment
...
Board check: Data are routed to output LED (falling edge data on LED1 + rising edge data on LED2).
MappingDirective
BlackBox
Description:
The user can declare a component which is a blackbox and map it into the desired NanoXplore macro cell using addBlackbox NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | addBlackBox |
Table: MappingDirective Blackbox environment
...
Board check: No board purpose for this testcase.
Memory
Description:
The user can map inferred operations into the desired NanoXplore macro cell using addMappingDirective NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | addMappingDirective getModels |
Table: MappingDirective Memory environment
...
Board check: No board purpose for this testcase.
Operator
Description:
The user can map inferred operations into the desired NanoXplore macro cell using addMappingDirective NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | addMappingDirective getModels getInstances |
Table: MappingDirective Operator environment
...
Board check: No board purpose for this testcase.
Pad
Parameter
Description:
The user can configure pads with many parameters using addPad or modifyPad NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP |
|
Methods | addPad |
Table: Pad Parameter environment
...
Board check: No board purpose for this testcase.
Registered
Description:
The user can map registers, mapped by default in NX_DFF and located in tiles, into NX_DFR located in the pad using addPad NXpython method and registered parameter.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP |
|
Methods | addPad |
Table: Pad Registered environment
...
Board check: No board purpose for this testcase.
PlacingConstraint
Aperture
Description:
The user can focus its design into a defined area using setAperture modifyAperture NXpython method.
Hereafter an example for this method:
| Code Block |
|---|
p.setAperturemodifyAperture(8,1,125,6) |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods |
modifyAperture |
Table: PlacingConstraint Aperture environment
...
Board check: No board purpose for this testcase.
ConstrainPath
Description:
The user can confine the path between registers in a region using constrainpath NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | constrainPath |
Table: PlacingConstraint ConstrainPath environment
...
Board check: No board purpose for this testcase.
...
ExportSites
Description:
The user can place manually a DSP using addDSPLocation export placing constraints (setSite, …) using exportSites NXpython method.
The exported file can be executed in another project in order to keep placing constraint of the project constraints were exported.
Hereafter an example for this method:
| Code Block |
|---|
p.addDSPLocationexportSites('*DSP_mult_L28*p','CGB[8x8]:RexportSitesFile.py') |
addDspLocation uses wildcard format.
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods |
exportSites |
Table: PlacingConstraint DspLocation ExportSites environment
Option: There is one option to check the impact of this constraint:
No option: The DSP is automatically placed by the toolProject is executed without placing constraints.DspLocation: The DSP is placed into the specified CGB and side
ExportSites: Exported constraints are used.
NanoXmap check: After project launching, the user can check in the GUI that the DSP is placed into the specified CGB and side.
...
constraints impact the design placing.
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
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Focus
Description:
The user can export placing constraints (setSite, addRAMLocation,…) using exportSites focus its design around a point using setFocus NXpython method.
The exported file can be executed in another project in order to keep placing constraint of the project constraints were exported.
Hereafter an example for this method:
| Code Block |
|---|
p.exportSitessetFocus('p','exportSitesFile.py'24,2) |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods |
setFocus |
Table: PlacingConstraint ExportSites Focus environment
Option: There is one option to check the impact of this constraint:
No option: Project is executed without placing constraintsA default focus is set by the tool.ExportSites: Exported constraints are used
Focus: A focus is set to the tool.
NanoXmap check: After project launching, the user can check in the GUI constraints impact the design placing.that all synthesized elements are gathered around the specified point.
...
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
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Obstruction
Description:
The user can focus its design around a point using setFocus remove regions from available area in the tool using addObstruction and modifyObstruction NXpython method.
Consequently, all included resources in the specified regions cannot be used for the design.
Hereafter an example for this method:
| Code Block |
|---|
p.setAperture(8,1,12,6addObstruction('OBSTR_0', 14, 6, 1, 3) p.modifyObstruction('OBSTR_0', 13, 5, 2, 4) |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods |
addObstruction modifyObstruction |
Table: PlacingConstraint Focus Obstruction environment
Option: There is one option to check the impact of this constraint:
No option: A default focus is set by the tool.Aperture: A focus is set to the toolThe whole area is available to place elements.
Obstruction: The specified region is not available to place elements.
NanoXmap check: After project launching, the user can check in the GUI that all synthesized elements are gathered around the specified pointarea cannot be used.
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Simulation check: No simulation environment is available for this testcase.
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Board check: No board purpose for this testcase.
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PreplaceIp
Description:
The user can remove regions from available area in the tool using createObstruction preplace an IP and declare IP as a blackbox using addBlackBox NXpython method.
Consequently, all included resources in the specified regions cannot be used for the design.
Hereafter an example for this method:
| Code Block |
|---|
p.createObstruction('OBSTR_0', 14, 6, 14, 8) |
Environment:
Here after the table of compliances for this testcase.
...
Variant
...
NG-MEDIUM NG-LARGE NG-ULTRA
...
Embedded
...
Yes
...
Simulation
...
No
...
Attributes
...
...
IP
...
...
Methods
...
createObstruction
Table: PlacingConstraint Obstruction environment
Option: There is one option to check the impact of this constraint:
No option: The whole area is available to place elements.
Obstruction: The specified region is not available to place elements.
NanoXmap check: After project launching, the user can check in the GUI that the specified area cannot be used.
...
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
PreplaceIp
Description:
The user can preplace an IP and declare IP as a blackbox using addBlackBox NXpython method.
It is necessary to comply with the following rules:
Set the minimum aperture to the IP.
Declare the IP as a blackbox in the top project by adding the previous IP files.
Set starting point Column x Row of the instance to a similar element (ex: TILE) than the IP aperture starting point.
Save IP project file used in the top project file after end of routing.
In the top project, IP is declared as a module and the aperture and the starting point are used in order to compute the associated region.
Hereafter an example for this method:
| Code Block | ||
|---|---|---|
| ||
p.addBlackBox('switch_counter',IP','../switch_counter_preplaced.nym','g_inst.i_switch_counter_0:1x8') |
| Note |
|---|
Some instances of the ring and the fabric are not supported yet. Please refer to https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/48660481. |
Environment:
Here after the table of compliances for this testcase.
...
Variant
...
NG-MEDIUM NG-LARGE NG-ULTRA
...
Embedded
...
Yes
...
Simulation
...
No
...
Attributes
...
...
IP
...
...
Methods
...
addBlackBox setAperture
Table: PlacingConstraint PreplaceIp environment
Option: There is one option to check the impact of this constraint:
No option: No IP is used, VHDL files are used for synthesis.
Preplace: Preplaced IP is used.
NanoXmap check: After project launching, the user can check in hierarchy.rpt that the IP is seen as a module.
...
Simulation check: No simulation environment is available for this testcase.
Board check: No board purpose for this testcase.
RamLocation
Description:
The user can place manually a RAM using addRAMLocation NXpython method.
Hereafter an example of using this method:
| Code Block |
|---|
p.addRAMLocation('g_loop[0].i_RAM_example|s_mem*','CGB[8x8]') |
...
It is necessary to comply with the following rules:
Set the minimum aperture to the IP.
Declare the IP as a blackbox in the top project by adding the previous IP files.
Set starting point Column x Row of the instance to a similar element (ex: TILE) than the IP aperture starting point.
Save IP project file used in the top project file after end of routing.
In the top project, IP is declared as a module and the aperture and the starting point are used in order to compute the associated region.
Hereafter an example for this method:
| Code Block | ||
|---|---|---|
| ||
p.addBlackBox('switch_counter',IP','../switch_counter_preplaced.nym','g_inst.i_switch_counter_0:1x8') |
| Note |
|---|
Some instances of the ring and the fabric are not supported yet. Please refer to https://nanoxplore-wiki.atlassian.net/wiki/spaces/NAN/pages/48660481. |
Environment:
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods |
addBlackBox modifyAperture |
Table: PlacingConstraint RamLocation PreplaceIp environment
Option: There is one option to check the impact of this constraint:
No option: The RAM is automatically placed by the tool.RamLocation: The RAM is placed into the specified CGBNo IP is used, VHDL files are used for synthesis.
Preplace: Preplaced IP is used.
NanoXmap check: After project launching, the user can check in the GUI hierarchy.rpt that the DSP is placed into the specified CGBIP is seen as a module.
...
Simulation check: No simulation environment is available for this testcase.
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Board check: No board purpose for this testcase.
Region
Description:
The user can confine a module in a region using addModule, createRegion addRegion and confineModule or directly constrainModule NXpython methods.
...
| Code Block |
|---|
p.addModule('up_counter','GEN_HIER2.COUNTER0','GEN_HIER2_COUNTER0-%','Soft')
p.createRegionaddRegion('HIER2_COUNTER0', 13, 6, 142, 83,False)
p.confineModule('GEN_HIER2_COUNTER0-0', 'HIER2_COUNTER0') |
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods |
addRegion removeRegion modifyRegion addModule confineModule constrainModule removeSoftModules |
Table: PlacingConstraint Region environment
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Board check: No board purpose for this testcase.
RingLocation
Description:
The user can place manually PLL and WFG into a CKG using respectively addPLLLocation and addWFGLocation NXpython methods. The method addRingLocation can be used too in both cases.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | addWFGLocation addPLLLocation addRingLocation |
Table: PlacingConstraint RingLocation environment
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Board check: No board purpose for this testcase.
Site
Description:
The user can place manually a register into a tile fabric element (LUT, DFF, RF, CY, RAM,DSP) into a TILE/CGB using setSite NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | setSite clearFabricPrePlaceConstraints |
Table: PlacingConstraint Site environment
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Board check: No board purpose for this testcase.
ProcessingSystem
Interruptions
Description:
The user can generate interruptions from the Fabric to the SoC through SoC interface.
...
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_SOC_INTERFACE |
Methods |
Table: ProcessingSystem Interruptions environment
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Board check: Check interruptions are received by the SoC when using switches.
Watchdog
Description:
The user can use watchdogs from processing system cores.
...
Here after the table of compliances for this testcase.
Variant | NG-ULTRA |
Embedded | No |
Simulation | No |
Attributes |
|
IP | NX_SOC_INTERFACE |
Methods |
Table: ProcessingSystem Interruptions environment
...
Board check: Check LED associated to the programmed watchdog is switched when watchdog counter limit is reached.
StaConstraint
CaseAnalysis
Description:
The user can specify a case analysis for the STA using setCaseAnalysis NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | setCaseAnalysis createClock setClockGroup getClockNet getNet |
Table: StaConstraint ClockGroup environment
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Board check: No board purpose for this testcase.
ClockGroup
Description:
The user can specify unrelated clocks using setClockGroup NXpython method or calling SDC constraint.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock setClockGroup getClock |
Table: StaConstraint ClockGroup environment
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Board check: No board purpose for this testcase.
DelayPath
Description:
The user can specify path delays between registers by using addMinDelayPath, addMaxDelayPath and addMulticyclePath NXpython methods or calling SDC constraints.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | addMaxDelayPath addMinDelayPath addMulticyclePath getRegister |
Table: StaConstraint DelayPath environment
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Board check: No board purpose for this testcase.
FalsePath
Description:
The user can specify path to be ignored by the STA by using addFalsePath, NXpython method or calling SDC constraint.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA | |
Embedded | Yes | |
Simulation | No | |
Attributes |
| |
IP |
| |
Methods | addFalsePath getRegister getRegisters getRegistersByClock getPort createClock |
Table: StaConstraint FalsePath environment
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Board check: No board purpose for this testcase.
GeneratedClock
Description:
The user can create a clock directly or specifying its relationship with another clock using respectively createClock and createGenerateClock NXpython method.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock createGeneratedClock getPort getClockNet getRegisterClock |
Table: StaConstraint GeneratedClock environment
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Board check: No board purpose for this testcase.
InputOutputDelay
Description:
The user can apply a minimum and a maximum data arrival time on inputs and outputs using respectively setInputDelay and setOutputDelay NXpython methods.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock getPort getPorts getClock setInputDelay setOutputDelay |
Table: StaConstraint InputOutputDelay environment
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Board check: No board purpose for this testcase.
ReportPath
Description:
The user can generate timing reports between two pins or two registers with respectively reportPath or addReportPath and reportTiming or addReportTimingPath NXpython methods.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock reportPath addReportPathRequest reportTiming addReportTimingRequest removeReportPathRequest removeReportTimingRequest clearTimingConstraints getRegister getPin getPort getProject getAnalyzer |
Table: StaConstraint ReportPath environment
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Board check: No board purpose for this testcase.
SpacewireTiming
Description:
The user must be able to get all needed timing in case of recovery clock like Spacewire one.
...
Here after the table of compliances for this testcase.
Variant | NG-MEDIUM NG-LARGE NG-ULTRA |
Embedded | Yes |
Simulation | No |
Attributes |
|
IP |
|
Methods | createClock |
Table: StaConstraint SpacewireTiming environment
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