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Copyright
All the contents of this document are protected by the copyright law. They may not be disclosed to third parties or copied or duplicated in any form without consent of NanoXplore.
Introduction
Aim of document
This document is intended to guide users on NXmap software best practice.
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For any kind of help, please contact NanoXplore support team at support@nanoxplore.com.
Content
All recommendations are divided in several categories depending on product development phase.
They are based mainly on NXpython methods but some of them can be applied in the GUI.
Design
NanoXplore primitive instantiation
All NanoXplore primitives are listed in nxLibrary-<variant_name>.vhdp available in the release archive. A documentation is also available in order to get information about all generics and io in https://nanoxplore-wiki.atlassian.net/wiki/spaces/SANDBOX/pages/202244165.
It is recommended to only add the nxpackage in the work library and not component declarations as they are already declared in the package.
Clock management
NanoXplore FPGAs contain a low-skew network in order to spread signal with high fanout like clock, reset, load signals.
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Please have a look at Training Package Application Note Design/LowskewManagement project.
Reset management
Like clocks, reset are generally spread to the whole design through the low-skew network because of high fanout too.
Reset can be asynchronous or synchronous as registers of NanoXplore FPGAs are compliant with both.
It is recommended to code with active high reset as all NanoXPlore primitives are active high reseted. Otherwise, a LUT used as an inverter will be instantiated before going to the low-skew network.
Global signals management
There are some signals with high fan out can be mapped into low-skew network and introduced some important delays. It could be the problem with synchronous signals load, set, reset, …
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p.rejectLowskew('inst1|reset_sync') |
Memory initialization
There are several ways to initialize a memory (attribute, generic, python method).
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Please have a look at Training Package Application Note Init/Ram project.
Memory Inference
In order to infer a memory instead of instantiating a NanoXplore primitive (advantage is the user can choose with the same RTL code to map this memory in RF, RAM, RAM_ECC, … thanks to NXpython constraints), it is recommended to follow TrainingPackage Design/MemInfer examples providing inference for ROM, SRAM, DPRAM with and without ECC.
Please have a look at Training Package Application Note Design/MemInfer project.
Hierarchy
It is recommended to divide the design in well sized modules depending on the function they are responsible for.It will be very helpful to constrain the design by module then
It will be very helpful to constrain the design by module then.
Logic depth
It is highly recommended to avoid large logic depth between registers as it will limit the maximum frequency of the design.
In addition, when a LUT is used, the DFF from the same Functionnal Element will be used either as a register or a buffer so adding pipeline in the design won’t consume any additional instance.
Project creation
NXmap is based on Python scripts that is to say a project is a class and all options and constraints are methods associated to this class.
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Set options before any progress.
Set IO pads locations and parameters before any progress.
Save your project after each progress step.
Separate your project in categories (setup,synthesis, placing, routing, sta) and set your constraints at the right place.
Project check
Once the project is launched, it is necessary to check logs and reports in order to be sure there is not any issue leading to errors, undesired optimizations, …
Logs and report files analysis
Errors and warnings
First of all, check the project is successful until the required progress step.
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Even though the project is successful, it is advised to parse these files.
Complexity
After errors and warnings are solved or understood, check hierarchy.rpt and progress.rpt in order to check the number of instances is relevant with the estimation.
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Refer to #Floor_planning_Complexity for more details.
IO Location
Check in progress.rpt none IO has been automatically placed by the design. It is marked with an exclamation sign.
Common Errors
There are typical types of errors :
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If modules are constrained with constrainModule method, increase area size
Change the Seed used for P&R
Change the following options: CongestionEffort, DensityEffort, RoutingEffort
STA
Once the project is mature enough, Static Timing Analysis can be done in order to check how fast the design can operates.
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It is advised to launch a STA after Preparing as it shows up most critical paths and the maximum frequency with most optimistic hypothesis. If maximum frequencies are not higher enough at this step, it won’t be after routing for sure.
Clock creation
The input clock frequencies and other parameters must be informed to NXmap for STA.
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If a PLL is used, PLL output clock frequencies are automatically computed by the software.
Special path and clock domains relationship
Declare all false paths and multi cycle paths in order to not take into account some paths between registers in some particular cases.
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Clock groups can be created if clock domains are completely unrelated.
Timing files analysis
When launching the STA tool, the following files are created :
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Use the first 3 timing files in order to get an overview of the project and other ones to analyze paths.
Optimization
Mapping
Operator
Operators are divided in 3 categories :
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Check #Mapping_Directive_Operator for information about constraint setting.
Memory
Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction thanks to addMappingDirective method described in /wiki/spaces/~814749387/pages/48660481.
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Check #Mapping_Directive_Memory for information about constraint setting.
Placing
In order to improve the maximum clock frequency for each clock domain, it is advised to follow the following steps:
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addPLLLocation for PLL instance in a CKG. Check #Instance_placing_Ring_placing for information about constraint setting.
addWFGLocation for WFG instance in a CKG and a WFG spot. Check #Instance_placing_Ring_placing for information about constraint setting.
addRAMLocation for RAM instance in a CGB. Check #Instance_placing_Ram_placing for information about constraint setting.
addDSPLocation for DSP instance in a CGB and a DSP spot. Check #Instance_placing_Dsp_placing for information about constraint setting.
setSite for LUT/DFF/CY in a TILE. Check #Instance_placing_Tile_placing for information about constraint setting_placing_Tile_placing for information about constraint setting.
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The logic depth of a design must be controlled. the method reportDesignComplexity is very helpful to have an overview.
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Please have a look at NxBeta_NXpython specification reportDesignComplexity method.
How to use NXpython constrains methods
Mapping directive
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In order to map an operator into LUT, CY or DSP, follow the following steps:
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Please have a look at Training Package Application Note MappingDirective/Operator project.
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In order to map an operator into FE, RF, RAM or RAM_ECC, follow the following steps:
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Please have a look at Training Package Application Note MappingDirective/Memory project.
Instance placing
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In order to place manually an inferred DSP in a CGB spot, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/DspLocation project.
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In order to place manually an inferred RAM in a CGB spot, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/RamLocation project.
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In order to place manually an automatically created WFG in a CKG spot, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/RingLocation project.
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In order to place manually an inferred TILE instance like DFF, LUT or CY, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/Site project.
Floor planning
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In order to get complexity for each module of the design, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/Region project.
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In order to confine a module (component of the design hierarchy) in a region containing TILE, CGB and MESH, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/Region project.
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In order to confine all instances in a path between 2 registers in a region containing TILE, CGB and MESH, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/ConstrainPath project.
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In order to preplace a macro IP of a global design in order to reach design specifications (delays, maximum frequencies, …) in an area of the chip before integrating it in the global design, follow the following steps:
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Please have a look at Training Package Application Note PlacingConstraint/Preplace project.
STA constraints
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In order to declare a clock in your project in order to get required frequencies in logs, follow the following steps:
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Please have a look at Training Package Application Note StaConstraint/GeneratedClock project.
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In order to declare a clock in your project in order to get required frequencies in logs, follow the following steps:
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Please have a look at Training Package Application Note StaConstraint/GeneratedClock project.
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In order to declare a path between 2 registers as a false path, multi-cycle path, min or max delay path, follow the following steps:
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Please have a look at Training Package Application Note StaConstraint/FalsePath project.
How to improve STA results
STA tool
It is recommended to launch the STA tool after Placing 1/5 step named “Preparing”. It allows to witness the number of logic elements crossed and check if it is possible to reach performances when the margin in the most optimistic scenario is high enough.
ClockCreation
Before launching STA tool, all constraints must be defined.
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createClock for clock coming from a port. Refer to #Sta_constraints_Clock_creation.
createGeneratedClock if a clock is generated inside the fabric. Refer to #Sta_constraints_Generated_clock_creation.
addFalsePath in order to remove paths to ignore. Refer to #Sta_constraints_Path_between_registers.
TimingDriven
TimingDriven option can be set with the following constraint:
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The TimingDriven efficiency is in continuous development and improvement. |
Floor planning
In order to give indications to the tool, the user can set up a floor-planning and pass it through the tool working directly on the whole design or working with unitary runs before integrating in the top design as specified in #Floor_planning_Preplace_ip.
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With this solution, the user must pay attention to interconnections between modules and between module and output interfaces. |
Logic depth reducing
The highest the required frequency is, the lowest the number of combinatorial elements between 2 registers must be.
It can be iterative to control the logic depth of a design by using the method explained in #Design_complexity and adapt the code if the required frequency cannot be achieved.