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Comment: add info about BinarySafe

...

Méthod

Project

Synthesize

Place & Route

Bitstream

STA

Simulation

addADCLocation

X

addBank

 

 

 

X

 

 

addBanks

 

 

 

X

 

 

addBlackBox

 

X

 

 

 

 

addDACLocation

X

addFalsePath

 

 

 

 

X

X

addFile

X

 

 

 

 

 

addFiles

X

 

 

 

 

 

addHSSLLocation

addIP

X

 

 

 

 

 

addMappingDirective

 

X

 

 

 

 

addMaxDelayPath

 

 

 

 

X

X

addMemoryInitialization

 

 

 

X

 

 

addMinDelayPath

 

 

 

 

X

X

addModule

 

X

 

 

 

 

addMulticyclePath

 

 

 

 

X

X

addObstruction

X

addPLLLocation

 

 

X

 

 

 

addPad

 

X

X

 

 

 

addPads

 

X

X

 

 

 

addParameter

X

 

 

 

 

 

addParameters

X

 

 

 

 

 

addPin

 

X

X

 

 

 

addPins

 

X

X

 

 

 

addRegion

X

addRingLocation

 

 

X

 

 

 

addRingLocations

 

 

X

 

 

 

addVerilogIncludeDirectories

X

 

 

 

 

 

addVerilogIncludeDirectory

X

 

 

 

 

 

addVlogDefine

X

 

 

 

 

 

addVlogDefines

X

 

 

 

 

 

addWFGLocation

 

 

X

 

 

 

applySdcFileimportSdcFile

 

 

 

 X

 

clearBanks

 

 X

 

 

 

clearFabricPrePlaceConstraints

X

clearPLLs

 

X 

 

 

 

clearPads

 

X

 

 

 

clearPins

 

X

 

 

 

clearWFGs

 

X 

 

 

 

confineModule

 

 

X

 

 

 

constrainModule

 

X

X

 

 

 

constrainPath

 

X

X

 

 

 

createAnalyzer

 

 

 

 

X

 

createClock

 

 

 

 

X

 

createGeneratedClock

 

 

 

 

X

 

createSimulator

 

 

 

 

 

X

destroy (project)

X

 

 

 

 

 

destroy (analyzer)

X

developCKGs

 

 

 

 

X

 

exportAsIPCore

X

 

 

 

 

 

exportPlacement

X

exportRegions

X

 

 

 

 

 

exportSites

X

 

 

 

 

 

generateBitstream

 

 

 

X

 

 

generateSTANetlist

X

 

 

 

 

 

getAnalyzer

X

getDirectory

X

 

 

 

 

 

getErrorCount

X

getHierInfo

X

getLowskewSignals

X

 

 

 

 

 

getProject

X

getRemarkCount

X

getTimingUnit

X

 

 

 

 

 

getTopCellName

X

 

 

 

 

 

getVariantName

X

 

 

 

 

 

getWarningCount

X

importPlacement

X

initRegister

 

 

 

X

 

 

limitLowskew

 

 

injectLowskew

X

 

 

 

listAvailableLocations

X

 

 

 

 

 

load

X

 

 

 

 

 

modifyAperture

X

modifyObstruction

X

modifyPad

X

modifyRegion

 

 

X

 

 

 

place

X

 

 

 

 

 

progress

X

 

 

 

 

 

printError

X

printHierInfo

X

printRemark

X

PrintText

X

PrintWarning

X

rejectLowskew

 X

 

X

 

 

 

removeFile

X

 

 

 

 

 

removeFiles

X

 

 

 

 

 

removeObstruction

X

removeRegion

X

removeSoftModules

X

reportDesignComplexity

X

reportHierarchyComplexity

X

reportInstances

X

 

 

 

 

 

reportLowskewSignals

X

 

 

 

 

 

reportPorts

X

 

 

 

 

 

reportRegions

X

 

 

 

 

 

reportRegisters

X

 

 

 

 

 

resetTimingConstraints

X

 

 

 

 

 

route

X

 

 

 

 

 

save

X

 

 

 

 

 

setAnalysisConditions

 

 

 

 

X

 

setCaseAnalysis

 

 

 

 

X

 

setClockGroup

 

 

 

 

X

 

setDescription

X

 

 

 

 

 

setDeviceID

 

 

 

X

 

 

setDirectory

X

 

 

 

 

 

setFalsePath

 

 

 

 

X

 

setFocus

 

 

X

 

 

 

setGCKCount

 

 

X

 

 

 

setInputDelay

 

 

 

 

X

 

setMaxDelay

 

 

 

 

X

 

setMinDelay

 

 

 

 

X

 

setMulticyclePath

 

 

 

 

X

 

setOption

X

 

 

 

 

 

setOptions

X

 

 

 

 

 

setOutputDelay

 

 

 

 

X

 

setSite

 

 

X

 

 

 

setTopCellName

X

 

 

 

 

 

setVariantName

X

 

 

 

 

 

synthesize

X

 

 

 

 

 

...

Type

Mapping targets

ADD

LUT, CY, DSP

LTN

LUT, CY, DSP

MUL

CY,DSP

RAM

DFF, RF, RAM, RAM_ECC, DFFRAM_ECC_SLOW

ROM

LUT, RF, RAM, RAM_ECC, RAM_ECC_SLOW

Instance name must match the following pattern: ‘PATHNAME|INSTANCENAME’

Note

RAM_ECC_SLOW is not only available for NG-MEDIUM/NG-LARGE

Example:

If the HDL design named myTest contains a small 3 write ports and 3 read ports FIFO named myFifo, nxpython cannot automatically map it into RF or RAM, but user can add a mapping directive to map it into DFF:

...

Note

Check chip datasheet to see differential feature availability on different IO banks.

Info

In case of not compliant VICM typical value with LVDS external device, VT can be set with LVDS differential mode. Refer to LVDS input common mode application note.

Unit of inputSignalSlope key is V/ns in the range [0.5;20] (Default 0).

...

Code Block
languagepy
project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)

...

importSdcFile(filePath)

This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.

...

Code Block
languagepy
project.applySdcFileimportSdcFile(./sdc_directory/constraints.sdc)

...

Code Block
breakoutModewide
languagepy
project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'),getRegister('data_reg[0]'), 'clk1_div2', {'DivideBy': 2})

destroy() (project)

This method is used to destroy the project.

...

Code Block
Display after destruction
Traceback (most recent call last):
    File "test.py", line 22, in <module>
        project.display()
impulse.error: Invalid Request: Obsolete object

destroy() (analyzer)

This method is used to destroy the analyzer.

This method takes no argument.

Example:

Code Block
languagepy
a = project.createAnalyzer()
a.launch()
a.destroy()

display()

This method is used to open current project in impulse graphic user interface. It can be called several times from the same Python script.

...

Code Block
project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.initRegister('SPI_CTRL', '0x01f4003f')
project.generateBitstream('bitstream.nxb')

...

injectLowskew(signal, [lobes])

This method is used to limit inject a lowskew signal to be used in only signal in lowskew network in specified lobes.

Arguments:

Name

Type

Description

signal

string

name of the signal.

lobes

string

list of specified allowed lobes for the lowskew signals. Lobes must be separated by “,” character

Example:

Code Block
project.injectLowskew('clk')
project.limitLowskewinjectLowskew('clk_right','Rx1,Rx2,Rx3,Rx4')

...

Name

Default

Description

'AllowCascadedGCK'

‘No’

‘No’: Prohibit GCK cascade

‘Yes’: Allow GCK cascade

'Autosave'

'Yes'

Enable automatic protect save after each flow step.

'BypassingEffort'

'Medium'

Specify the DFF load and reset spreading level into the low-skew network (can be 'Low', 'Medium' or 'High'):

Low: all Load and Resetare sent in low skew

Medium: Impulse choose an effective balance

High: all Load and Reset are routed in common parts ( high routing constraint)

'CMICLatency'

'0'

Additional delay between 2 CMIC scans.

Expressed Integer value expressed in number of BSM clock cycles.

Total delay between 2 scans is:

(CMICLatency+1) * 2**16

'CongestionEffort'

'High'

Specify the routing resources limit per tile to leave and enter in the tile (can be 'Low', 'Medium' or 'High'):

  •         Low : less routing constraints but may need further more tiles and CGBs

  •         Medium : balanced routing constraints but may need more tiles and CGBs

  •         High : all routing resources

'Dynamic'

'No'

Refresh view while algorithms are running.

'DefaultFSMEncoding'

'OneHot'

Default encoding of finite state machine (can be 'OneHot', 'OneHotSafe', 'OneHotSafeExtra' or 'Binary'):

  •        Binary: minimum amount of bit is used (when others clause is used the mode is implicitly BinarySafe)

  •        OneHot: only one bit changes per state. Others case is not handled.

  •         OneHotSafe: detects invalid state where all bits are ‘0’ and returns to others case.

  •         OneHotSafeExtra: detects any invalid state where all bits are '0' or more than one bit to ‘1’ and returns to others case. Additional logic is implemented.

Example for binary encoding with 3 states:

Code Block
“00”, “01”, “10”

Example for one hot encoding with 3 states:

Code Block
“001”, “010”, “100”
Note

If state encoding is forced by the RTL code with the following example, the FSM is not reported in logs:

attribute enum_encoding of t_state_type : type is "01 10"

'DefaultRAMMapping'

'AUTO'

Default mapping of RAM (can be 'AUTO', 'RF', 'RAM' or 'RAM_ECC').

'DefaultROMMapping'

'AUTO'

Default mapping of ROM (can be 'AUTO', 'LUT', 'RF', 'RAM' or 'RAM_ECC').

'DensityEffort'

'Low'

Specify the tile instance resources allowed per tile like DFF,LUT, … (can be 'Low', 'Medium' or 'High'):

  • Low: less resources (less routing constraints but may need more tiles and CGBs): 70% is allowed

  • Medium: well suited resources: 80% is allowed

  • High: more resources (more routing constraints): 90% is allowed

'DisableAdderBasicMerge'

'No'

Disable carry optimization around adders and subtractors.

'DisableAdderTreeOptimization'

'No'

Disable adder mux reordering and adder tree balancing.

'DisableAdderTrivialRemoval'

'No'

Disable simplification of adder that could fit in 1 or 2 LUTs.

'DisableAssertionChecking'

'No'

Deactivate VHDL assertions.

'DisableDSPAluOperator'

'No'

Disable merge of ALU within inferred DSP.

'DisableDSPFullRecognition'

'No'

Disable inference of DSP.

'DisableDSPPreOperator'

'No'

Disable merge of pre-operator within inferred DSP.

'DisableDSPRegisters'

'No'

Disable merge of registers within inferred DSP.

'DisableRegisterMergeInDspForAdd'

‘No’

Disable merge of registers in DSP when used as adder

'DisableKeepPortOrdering'

'No'

Disable keep port ordering used in source files when generating HDL netlists.

'DisableLoadAndResetBypass'

'No'

Disable load and reset signal bypass on DFF.

'DisableRAMAlternateForm'

'No'

Disable recognition of registered address read port.

'DisableROMFullLutRecognition'

'No'

Disable merge of ROM recognized as LUT with logic.

'DisableRAMRegisters'

'No'

Disable merge of registers within inferred RAM.

‘ExhaustiveBitstream’

‘No’

Can be used to force generation of all configurations and contexts in bitstream (can be ‘No’, ‘Config’, ‘Context’ or ‘ConfigContext’).

'GenerateBitstreamCMIC'

'No'

Generate bitstream with CMIC.

‘InitializeContext’

'No'

Initialize all DFF, RFB and RAM of the chip.

It increases the bitstream size.

'IgnoreRAMFlashClear'

'No'

Do not output error when recognizing a RAM with flash clear.

'ManageAsynchronousReadPort'

'No'

If 'Yes', detect asynchronous read port in memories and repair it in synchronous read port. The read port receive the reversed write clock. It can slow down the design and sometimes may cause invalid behavior.

'ManageUnconnectedOutputs'

'Error'

Undriven outputs of HDL modules are treated as ‘Error', 'Ground', 'Power' or 'Preserve’.

Error: Generates an error

Ground: Connect to '0'

Power: Connect to '1'

Preserve: Preserve attribute set to avoid optimization

'ManageUnconnectedSignals'

'Error'

Undriven internal signals of HDL modules are treated as ‘Error', 'Ground', 'Power' or 'Preserve’.

Error: Generates an error

Ground: Connect to '0'

Power: Connect to '1'

Preserve: Preserve attribute set to avoid optimization

'ManageUninitializedLoops'

'No'

Remove reset-less looped DFF causing extra-mapping and 'X' values in simulation (can be 'No', 'Power, ''Ground').

'MappingEffort'

'Low'

Effort for an optimized mapping in terms of primitive instance merging and simplification (can be 'Low', 'Medium' or 'High'):

  •         Low: almost no optimization

  •         Medium: balanced optimizations

  •         High: almost all optimizations

'MaxRegisterCount'

'2500'

Maximum number of registers handled per HDL module (not the whole design) by the synthesizer.

‘OptimizedMux’

‘Yes’

If set to 'Yes', impulse will identify and convert every mux in the corresponding optimized 4-LUT structure.

'PartitioningEffort'

'Medium'

Define the size of the netlist subset which will be further optimized for timing goals achievement (can be 'Low', 'Medium' or 'High') :

  •         Low: small part

  •         Medium: medium part

  • · High: huge part

Info

Option is activated only if TimingDriven option is enabled.

'PolishingEffort'

'Medium'

It allows to regenerate locally a signal in TILE which in normal way should be provide by an others TILE in order to reduce utilization of routing resources.

  • Low: deactivate

  • Medium: can replicate LUT

  • High: can replicate LUT and DFF

'ReadyOffWithSoftReset'

‘Yes’

Only available for NG-ULTRA variant.

It links the ready falling edge to soft reset enabling during the power off reset sequence.

‘ReplicationApproval’

‘Yes’

Allow replication in a close TILE if not possible in the current TILE.

  •         No: Do not allow replication

  •         Yes: Allow replication

'RoutingEffort'

'Medium'

Routing Optimization level in terms of routing instances (can be 'Low', 'Medium' or 'High'):

  •         Low: no optimization

  •         Medium: balanced optimizations

  •         High: further optimizations but time consuming

‘SaveTiming'

‘No’

Save STA in .nym project files

  •         No: STA is not saved in project files

  •         Yes: STA is saved in project files

‘Seed’

‘1789’

Seed for placing algorithm start. Depending on the seed, instances are created in a different order and placed so.

Can be used in order to generate several Place & Route with the same synthesized project.

'SetRunAfterContext'

‘No’

Indicate the sequence in the bitstream between run (routing instances enable) and context (initialization values for DFF, RFB, RAM).

  •         No: Run is set before Context

  •         Yes: Run is set after Context

'SharingEffort'

'Medium'

Enables the insertion in lowskew network signal with fanout above the SharingFanout threshold.

  • Low: Lowskew insertion disabled

  • Medium/High: Lowskew insertion enabled

Medium and High have the same impact.

'SharingFanout'

'100'

Fanout threshold to insert signal in lowskew network.

This option has an impact only if SharingEffort is set to Medium or High.

‘SimplifyRegions’

‘Yes’

Clear module and region database:

  • delete modules without instance

  • delete regions without module

  • merge identical regions

‘SytemOutputDriven’

'No'

Increase placing close to the ring for instances communicating with.

  •         No: No priority for these instances in algorithm

  •         Yes: Allow priority for these instances in alogrithm

'TimingEffort'

‘High’

Indicates level of iterations for TimingDriven algorithm.

  •         Low: no iteration

  •         Medium: a few iteration

  •         High: more iterations

Info

Option is activated only if TimingDriven option is enabled.

Note

For heavy designs, runtime can increase drastically depending on number of iterations.

'UnusedPads'

'Floating'

State in which the pads must be set when not used. Values can be 'Floating','WeakPullUp', 'WeakPullDown'. Note that when the state is different from 'floating', all the pads are serialized in the bitstream.

Note that ‘WeakPulldown’ value is not available on NX1H35S component.

‘VariantAwareSynthesis’

‘Yes’

If set to ‘Yes’ synthesis will automatically map to equivalent resource when specific resource is depleted. For example using DSP when there are no more CY available (can be ‘Yes’ or ‘No’).

...

Code Block
languagepy
simulator.addWaves([‘A’, ‘B’, ‘O’])

destroy()

This method is used to destroy the simulator object.

...

To run the simulation, the simulator object must be fully initialized. You must at least have specified the testbench files and the testbench top cell.tim

The simulation is launched on a netlist representing the current state of the project.

...

In impulse, data delay is the delay of a timing path. For example, the delay between the launch edge of the clock at the source register and data input pin of the destination register. In following picture, the path for the data delay between source register DFF1 and destination register DFF2 is shown in blue.

Anchor
Figure11
Figure11

...

Clock skew

Clock skew is the difference between the latch clock delay at the destination register and launch clock delay at the source register. Considering the example shown in previous figure, clock skew is calculated as follows:

...

            For example in following figure, three domains D1, D2 and D3 are shown between input and clock "clk" (D1: input to clk), between clock "clk" of source registers and clock "clk" of destination registers (D2: clk to clk), and between clock "clk" and output (D3: clk to output) respectively.

Anchor
Figure12
Figure12

...

Data arrival time

In impulse, data arrival time includes the overall data delay, clock skew and setup/hold time (recovery/removal) for a critical timing path in a domain. Based on the setup/hold verification, data arrival time can be either maximum or minimum. In both cases, data arrival time is calculated as follows:

...

Inthe following figure, hold and setup relationship is shown between a launch and latch clock with no skew. In case of having different frequencies for launch and latch clock, hold relationship is established between the active launch and latch edges with the minimum difference. Thus, hold relationship gives the minimum delay allowed between launch and latch edges. Whereas, the setup relationship is established between launch and latch edges with minimum difference, hence giving the maximum allowed delay between launch and latch edges.

Anchor
Figure13
Figure13

...

Case 2

If launch and latch clocks have active high and active low edges respectively, in this case hold relationship is established between active high launch edge and the previous active low latch edge with the minimum difference. Similarly, setup relationship is established between launch edge and the next latch edge with the minimum difference.

...

The following figure shows hold and setup relationship between active high launch clock and active low latch clock.

Anchor
Figure14
Figure14

...

Case 3

For the active low launch clock and active high latch clock, the hold relationship gives the minimum delay between active low launch edge and previous active high latch edge. Similarly, setup relationship gives the minimum delay between the active low launch edge and the very next active high latch edge as shown in the following figure.

Anchor
Figure15
Figure15

...

Case 4

If both launch and latch clocks have active low edges, the hold relationship is established between active low launch edge and previous active low latch edge. Similarly, setup relationship is established between the active low launch edge and the very next active low latch edge as shown in the following figure.

Anchor
Figure16
Figure16

...

Slack calculation

In impulse, setup/recovery slack corresponds to the difference between maximum setup/recovery relationship and maximum data arrival time whereas hold/removal slack corresponds to the difference between minimum data arrival and minimum hold/removal relationship.

...

Maximum Required Relationship

Anchor
Figure17
Figure17

...

  • The values of slack and of required relationship are only available for synchronous domains.

  • Maximum frequency is only computed for paths where the source and target registers are driven by the same clock.

...

  • Slack

  • Source (beginning of the path)

  • Target (ending of the path)

  • Data Delay

  • Clock Skew

  • Setup/Recovery (longest only)

  • Hold/Removal (shortest only)

  • Depth

  • Note (falling/rising edges of launch and latch clocks)

Anchor
Figure18
Figure18

...

Anchor
Figure19
Figure19

...

Path detail

Following the critical paths table, all the listed critical paths are reported in detail. For each part of the path, the table contents the following information: source (beginning of the path), target (ending of the path), routing delay, internal delay, cumulated delay (from the source of the path), setup/recovery time (for data path), hold/removal time (for data path), clock skew (for data path).

Anchor
Figure20
Figure20

...

Revision history

The following table shows the revision history of the Impulse_NXpython specification document:

ra_Date

Version

Revision

2022-12-15

1.0.1

Initial draft datasheet.