Introduction

These guidelines describe how to use the NX components provided in VHDL source code for Impulse and correctly instantiate the different supported NX components provided by NanoXplore for the Impulse Synthesis and Implementation tools.

A brief introduction and a description of both the generics and ports is included for each NX component along with a diagram of the component and an instantiation example in VHDL.

Clocks distribution and management

NX_BD

Description

The NX_BD component describes a Buffer Driver circuit that allows the user to direct the routing of a signal to the general routing or low-skew network.

Generics

system

mode string

default value “local_lowskew”

...

If mode is set to “global_lowskew”, the output signal is routed to global low skew network of fabric.

Ports

Example

This documentation only provides the instantiation of the component.

BD_0 : NX_BD

generic map (

      system => “global_lowskew”

port map (

      I => BUF_IN

    , O => BUF_OUT

);

NX_GCK_U

Description

The NX_GCK_U component describes a configurable ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is insignificant.

...

The NX_GCK_U can be used exclusively by instantiation. The current version of Impulse does not support inference for this device.

Generics

inv_in

type bit

default value ‘0’

This generic select wether to invert (inv_in = ‘1’) or not both clock inputs pins SI1 and SI2.

inv_out

type bit

default value ‘0’

This generic select wether to invert (inv_out = ‘1’) or not the clock output pin SO.

std_mode

type string

default value “BYPASS”

Select the configuration mode of the NX_GCK_U. NX_GCK_U can be configured into the following modes:

• BYPASS, where the SO output pin copies the clock input SI1.

• MUX, where the NX_GCK_U acts as a glitch free clock mux which allow to select with CMD pin either SI1 or SI2 clock signal to broadcast. In MUX mode, CMD=0 => SO=SI2 et CMD=1 => SO=SI1.

• CKS, where the NX_GCK_U is configured as a clock switch controlled by CMD pin to gate the SI1 input clock to be broadcast or not on SO output. In CKS mode, CMD=0 => SO=0 et CMD=1 => SO=SI1.

• CSC, where the NX_GCK_U is configured as common to system converter as the CMD input is copied on SO clock output. In CSC mode, SO=CMD.

Ports

Examples

This documentation only provides the instantiation of the component.

GCK_0 : NX_GCK_U

generic map (

    std_mode       => “MUX”,

    inv_in         => ‘0’  ,

    inv_out        => ‘0’ 

)

port map (

      SI1 => CK1

    , SI2 => CK2

    , CMD => ENABLE

    , SO  => CKG     -- SO <= SI1.CMD or SI2.not(CMD)

);



GCK_1 : NX_GCK_U

generic map (

    std_mode       => “MUX”,

    inv_in         => ‘0’  ,

    inv_out        => ‘1’ 

)

port map (

      SI1 => CK1

    , SI2 => CK2

    , CMD => ENABLE

    , SO  => CKG     -- SO <= not( SI1.CMD or SI2.not(CMD))

);

NX_CKS

Description

The NX_CKS component describes a ClocK Switch circuit that allows glitch free clock generation. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is insignificant. NX_CKS implements and automatically configures a NX_GCK_U primitive in CKS mode.

...

The blue internal signals are CMD signal sampled on rising edge (SPL1) and then sampled on falling edge (SPL0). SPL0 is the final enable.

Ports

Example

This documentation only provides the instantiation of the component.

CKS_0 : NX_CKS

port map (

      CKI => CK

    , CMD => ENABLE

    , CKO => CKG

);

NX_CMUX

Description

The NX_CMUX component describes a Clock mux circuit that allows glitch free clock selection between two input clock signals. It can be used to enable/disable the clock to part of the user’s logic – providing that the output signal will be glitch free – and the delay from the main clock to the generated one is insignificant. NX_CMUX implements and automatically configures a NX_GCK_U primitive in MUX mode.

...

The NX_CMUX can be used exclusively by instantiation. The current version of Impulse does not yet support inference for this device.

Ports

Example

This documentation only provides the instantiation of the component.

CMUX_0 : NX_CMUX

port map (

      CKI0 => CK0

    , CKI1 => CK1

    , SEL  => ENABLE

    , CKO  => CKG

);

NX_PLL_U

Description

The NX_PLL_U component describes a Phase Locked Loop circuit available in NG-ULTRA with an associated calibration delay module. The PLL just as the WaveForm Generators (WFG) is part of the ClocK Generator block (also called CKG). There are 7 CKG blocks in NG-ULTRA, 4 on in each corner of the FPGA die plus 2 on each side of the SoC and one at the center bottom of the FPGA die.

...

Figure 2: NG-ULTRA CKG block diagram

The next figure shows a block diagram of the NX_PLL_U and the user’s settings (in yellow).

...

Figure 3: Simplified NG-ULTRA PLL block diagram

Generics

location

type string

default value “”

This generic allows to define the NX_PLL_U location directly in the source code (instead of using the nxpython addPLLLocation method).

Example : location => “CKG2.PLL1”

use_pll

type bit

default value 0

Set to 1 to enable the PLL. When set to 0, the PLL is bypassed with Fvco = Frefo.

pll_odf

type bit_vector (1 downto 0)

default value others => ‘0’

Define the output division factor of the PLL (factors: 1, 2, 5 and 10).

pll_lock

type bit_vector (1 downto 0)

default value others => ‘0’

Configure the frequency lock.

ref_intdiv

type bit_vector (4 downto 0)

default value others => ‘0’

The REFerence frequency can be divided by factors ranging from 1 to 32 before reaching the VCO input. This allows to give more flexibility of the PLL generated output frequency, and increase the PLL input frequency range.

For VCO expected at 400MHz, ref_intdiv value must be set to 8 with a REF input frequency range between 45 and 450 Mhz.

ref_osc_on

type bit

default value ‘0’

This generic configures the source of the PLL reference.

If ref_osc_on is set to ‘0’, the input reference of the pll is the REF input pin.

If set to ‘1’, the internal oscillator is used as reference of the PLL.

ext_fbk_on

type bit

default value ‘0’

When ‘0’, the internal feedback path is selected. The output of the FBK_INTDIV divider is used as feedback source. The VCO output frequency is divided by (fbk_intdiv + 1)

When ‘1’, the external feedback path is selected. This is particularly useful for “zero delay” clock generation.

fbk_intdiv

type bit_vector (6 downto 0)

default value others => ‘0’

Internal feedback divider of N+1 ratio (with division from 1 to 128).

fbk_delay_on

type bit

default value ‘0’

This generic configures whether the delay of the feedback path is active (‘1’) or not (‘0’).

fbk_delay

type bit_vector (5 downto 0)

default value others => ‘0’

The number of delay taps on the feedback path (internal or external) can be adjusted to meet the required phase on the VCO outputs. When using external feedback, it can be used to compensate the delay on the reference clock input to the REF pin of the PLL via the semi-dedicated clock input pin and associated direct routing.

The delay can be selected or not (see fbk_delay_on). When selected, it can be adjusted from 340 ps (fbk_delay = 0) to 6740 ps (fbk_delay = 63) by steps of 100 ps.

clk_outdiv1 : applies to CLK_DIV1

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV1 = Fpll/(2*7+3) = Fpll / 17

clk_outdiv2 : applies to CLK_DIV2

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV2 = Fpll/(2*7+5) = Fpll / 19

clk_outdiv3 : applies to CLK_DIV3

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV3 = Fpll/(2*0+5) = Fpll / 7

If clk_outdiv3 = 7

CLK_DIV3 = Fpll/(2*7+5) = Fpll / 21

clk_outdiv4 : applies to CLK_DIV4

type bit_vector (2 downto 0)

default value others => ‘0’

...

CLK_DIV4 = Fpll/(2*0+5) = Fpll / 9

If clk_outdiv4 = 7

CLK_DIV4 = Fpll/(2*7+5) = Fpll / 23

clk_outdivd* : applies to CLK_DIVD*

type bit_vector (3 downto 0)

default value others => ‘0’

...

This generic allows to define the divider value of the CLK_DIVD* output. There are 16 possible values:

* clk_outdivd1/2/3/4/5 respectively apply to CLK_DIVD1/2/3/4/5

use_cal

type bit

default value ‘0’

When set to 0, the calibration module is bypassed. When set to 1, the calibration module is activated with cal_div and cal_delay generics used to define divide and delay values of the calibration engine.

clk_cal_sel

type bit_vector (1 downto 0)

default value “01”

Select the clock used for internal calibration.

cal_div

type bit_vector (3 downto 0)

default value “0111”

Set the division factor of the calibration engine.

cal_delay

type bit_vector (5 downto 0)

default value “011011”

Set the delay value of the calibration engine.

Notes about user’s adjustable delays on NG-ULTRA:

The PLL has a user’s selectable and adjustable delay line (no delay or 0 to 63 x 100 ps +/- 5% delay taps) on the feedback path. A similar delay chain is available in each WFGs. Finally, the IO banks have input, output and tri-state command 64-tap delay chains.

All the delay chain taps are calibrated with the same automatic process and hardware resources.

The procedure is transparent to the user.

The delays calibration system uses the PLL 400 MHz oscillator output as reference clock to calibrate all delays: feedback path in the PLL itself, WFG delays and calibration delay in same CKG), and IO delays in the neighboring complex IO banks:

• CKG1 oscillator calibrates the delays in CKG1 (PLL + CAL+ WFGs)

  • Banks 11 to 13

• CKG2 oscillator calibrates the delays in CKG2 (PLL + CAL + WFGs)

  • Banks 2 to 3

• CKG3 oscillator calibrates the delays in CKG3 (PLL + CAL + WFGs)

• CKG4 oscillator calibrates the delays in CKG4 (PLL + CAL + WFGs)

  • Banks 4 to 5

• CKG5 oscillator calibrates the delays in CKG5 (PLL + CAL+ WFGs)

Banks 8 to 10

• CKG6 oscillator calibrates the delays in CKG6 (PLL + CAL+ WFGs)

  • Banks 8 to 10

• CKG7 oscillator calibrates the delays in CKG7 (PLL + CAL+ WFGs)

  • Banks 11 to 13

The calibration procedure takes about 10 µs at startup. The “CAL_LOCKED” output goes high when the delay calibration process is complete. Can be used as status bit.

Ports

Instantiation Example

This documentation only provides the instantiation of the component.

-- In this example :

-- Fref = 96 MHz (and “ref_intdiv” = 11 for division factor of 12) 

-- Fvco = 417 MHz (96 MHz x 2 x (“fbk_intdiv” + 1) / (“ref_intdiv” + 1)) 

-- Fvco = 417 MHz (96 MHz x 2 x (24 + 1) / (11 + 1))

-- Please note that Fvco must be in the range 200 to 800 MHz 

-- Fdiv1 = 417 MHz / (2 * “clk_outdiv1” + 3) = 417 MHz / 7  = 59.52 MHz

-- Fdiv2 = 417 MHz / (2 * “clk_outdiv2” + 5) = 417 MHz / 11 = 37.88 MHz

-- Fdiv3 = 417 MHz / (2 * “clk_outdiv3” + 7) = 417 MHz / 13 = 32.05 MHz

-- Fdiv4 = 417 MHz / (2 * “clk_outdiv4” + 9) = 417 MHz / 15 = 27.78 MHz

-- Fdivd1 = 417 MHz / (“clk_outdivd1” ratio) = 417 MHz / 2    =   208 MHz

-- Fdivd2 = 417 MHz / (“clk_outdivd2” ratio) = 417 MHz / 8    =    52 MHz

-- Fdivd3 = 417 MHz / (“clk_outdivd3” ratio) = 417 MHz / 40   = 10.42 MHz

-- Fdivd4 = 417 MHz / (“clk_outdivd4” ratio) = 417 MHz / 80   =  5.21 MHz

-- Fdivd5 = 417 MHz / (“clk_outdivd5” ratio) = 417 MHz / 2000 = 0.208 MHz





PLL0 : NX_PLL_U 

generic map (

    location       => “CKG4.PLL1”, 

    ref_intdiv     => “01011”,    -- 0 to 31  ((N+1 : (%1 to %32)  -- 11 for div by 12 

    ref_osc_on     => '0',        -- 0: disabled - 1: enabled



    ext_fbk_on     => '0',        -- 0: disabled - 1: enabled



    fbk_intdiv     => “0011000”,  -- 0 to 31  ((N+1) : %4 to %66 by step 2)  -- Div by 25



    fbk_delay_on   => '0',        -- 0: no delay - 1: delay

    fbk_delay      => “000000”,   -- 



    clk_outdiv1    => “010”,      -- 0 to 7  D1 (2N+3)  -- Div by 7

    clk_outdiv2    => “011”,      -- 0 to 7  D2 (2N+5)  -- Div by 11

    clk_outdiv3    => “011”,      -- 0 to 7  D3 (2N+7)  -- Div by 13

    clk_outdiv4    => “011”,      -- 0 to 7  D4 (2N+9)  -- Div by 15

    clk_outdivd1   => “0000”,     -- 0 to 15  DIVD1     -- Div by 2

    clk_outdivd2   => “0011”,     -- 0 to 15  DIVD2     -- Div by 8

    clk_outdivd3   => “0110”,     -- 0 to 15  DIVD3     -- Div by 40

    clk_outdivd4   => “1000”,     -- 0 to 15  DIVD4     -- Div by 80

    clk_outdivd5   => “1111”      -- 0 to 15  DIVD5     -- Div by 2000

                              

   )

port map (

    REF   => REFIN,

    FBK   => FBK,



    R     => RST,

    ARST  => ARST,



    VCO   => VCO,              

    LDFO  => LDFO,             

    REFO  => REFO,

    

    CLK_DIV1 => DIV1,            

    CLK_DIV2 => DIV2,            

    CLK_DIV3 => DIV3,            

    CLK_DIV3 => DIV3,            



    CLK_DIVP1 => DIVP1,          

    CLK_DIVP2 => DIVP2,          

    CLK_DIVP3 => DIVP3,          

    CLK_DIVP4 => DIVP4,          

    CLK_DIVP5 => DIVP5,          

    OSC   => OSC,



    PLL_LOCKED  => PLL_LOCKED,

    PLL_LOCKEDA => PLL_LOCKEDA,

    CAL         => CAL,

    CAL_DIV     => CAL_DIV,

    CAL_LOCKED  => CAL_LOCKED

);

Simulation

The NX_PLL VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_PLL configurations.

NX_WFG_U

Description

The NX_WFG_U component is used to access the low skew lines and clock trees on NG-ULTRA. The NX_WFG_U is very similar to the NX_WFG_L of NG-LARGE. The difference is that the NX_WFG_U doesn’t have a RDY pin, only a R pin which can receive any external reset signal from the design and be internally combined with three other different sources of synchronization (coming from PLL lock output signals if one or several of the associated generics (reset_on_pll_lock_n, reset_on_pll_locka_n and reset_on_cal_lock_n) is set to 1. The NX_WFG_U also provides a full set of additional generic parameters.

...

Figure 4: NX_WFG_U diagram

Generics

location

type string

default value “” (no location constraint)

This generic allows to define the NX_WFG_L location directly in the source code (with the addWFGLocation method)

Example : location => “CKG2.WFG_C2”,

delay

type integer

default value 0

...

This generic configures whether the input clock is inverted (‘1’) or not (‘0’). When sampling the input clock, this generic configures whether the sampling is done on rising edge (‘0’) or falling edge (‘1’).

Ports

...

When sampling the input clock, the synchronization input must be connected either to another WFG (using pattern) synchronization output or the synchronization output of the WFG itself.

Example

This documentation only provides the instantiation of the component.

...

-- CK50MHz at 50 MHz

--   NOTCK   = ~CK50MHz

--   CK25MHz = CK50MHz / 2



WFG_0 : NX_WFG_U

generic map (

      location => “CKG1.WFG_C2”,

      wfg_edge => ‘1’

)

port map (

      SI => OPEN, SO => OPEN

    , ZI => CK50MHz, ZO => NOTCK

);



WFG_1 : NX_WFG_U

Generic map (

      location => “CKG1.WFG_C2”,

      mode    => ‘1’,

      div_ratio    => 0,

      div_phase    => ‘1’,

      pattern_end  => 1,

      pattern => b"1000000000000000"

)

port map (

      SI => SYNC, SO => SYNC

    , ZI => CK50MHz, ZO => CK25MHz

);

Simulation

The NX_WFG_U VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible NX_WFG_U configurations.

Core logic

NX_CY (!)

(!) : Important note : on Impulse, the NX_CY primitive includes only the dedicated arithmetic logic, excluding the Functional Element LUTs and FFs – unlike on Impulse, where the NX_CY primitive included the FE logic shown in dashed lines.

Description

The NX_ADD component describes a 4-bit adder and carry look ahead circuit. It’s available on the FEs having arithmetic logic capabilities.

The NX_ADD is composed of 4 stages numbered from 1 to 4 where 1 represents the LSB.

Figure 6: NX_ADD diagram

Generics

add_carry

type integer range 0 to 2

...

This generic represents the way the CI (carry in) port is connected: 0 is for low, 1 for high and 2 for propagate which means it is connected to the previous NX_CY CO (carry out) port.

Ports

Example

This documentation only provides the instantiation of the component..

-- SUM[3:0] <= A[3:0] + ”10”&B[1:0]



ADD_0 : NX_CY

generic map (

      add_carry   => 0                     -- low

)

port map (

      A1 => A(0), B1 => B(0)

    , A2 => A(1), B2 => B(1)

    , A3 => A(2), B3 => ‘0’

    , A4 => A(3), B4 => ‘1’

    , CI => OPEN, CO => OPEN

    , S1 => SUM(0), S2 => SUM(1), S3 => SUM(2), S4 => SUM(3)

);

NX_LUT

Description

The NX_LUT component describes a 4-input LUT as part of a functional element (FE) as shown in the following diagram:

Figure 7: NX_LUT diagram

Generics

lut_table

type bit_vector(15 downto 0)

...

• I4 and I3 and I2 and I1 => lut_table = b“1000000000000000” (or x”8000”)

• I4 or I3 or I2 or I1 => lut_table = b“1111111111111110” (or x”FFFE”)

• (I4 and I3) xor (I2 and I1) => lut_table = x”0111 1000 1000 1000” (or x”7888”)

Ports

Example

This documentation only provides the instantiation of the component.

LUT_0 : NX_LUT

generic map (

      lut_table => b“1000000000000000” -– O <= A and B and C and D

)

port map (

      I1 => A

    , I2 => B

    , I3 => C

    , I4 => D

    , O  => OUT

);

NX_DFF

Description

The NX_DFF component describes a DFF of the functional elements as shown in the following diagram:

...

Figure 8: NX_DFF diagram

Generics

dff_ctxt

type std_logic

default value ‘U’

...

This generic represents whether the reset must initialize the DFF to 0 or 1. dff_type is set to ‘0’ for reset initializing the DFF to 0, dff_type is set to ‘1’ for reset initializing the DFF to 1. dff_type can also be set to 2 to configure set/reset on signal.

Ports

Example

This documentation only provides the instantiation of the component.

...

DFF_0 : NX_DFF

generic map (

      dff_edge  => ‘0’                 -- rising edge

    , dff_load  => ‘0’                 -- always load

    , dff_init  => ‘1’                 -- use connected reset net

    , dff_sync  => ‘1’                 -- synchronous reset

    , dff_ctxt  => ‘0’                 -- initial value is 0

)

port map (

      I  => IN

    , O  => OUT

    , CK => CLK

    , R  => RST

    , L  => OPEN

);

NX_FIFO_U

Description

The NX_FIFO_U component provides a combination of two Register File Blocks circuit used as a base component for dedicated NX IPs defined for FIFO configuration of the RF with CDC (clock domain crossing) features: DPREG, XFIFO_64x18 (extended number of words) and 2 for XFIFO_32x36 (extended word size). Note that dedicated hard IPs are available for specific FIFO configurations : NX_XFIFO_64x18 and NX_XFIFO_32x36

Generics

wck_edge

type bit

default value ‘0’

...

This generic defines the desired FIFO configuration among: 0 for DPREG, 1 for XFIFO_64x18 (extended number of words) and 2 for XFIFO_32x36 (extended word size).

Ports

NX_FIFO_DPREG

Description

The NX_FIFO_DPREG is a wrapper component around NX_FIFO_U to have bus interfaces instead of bit to bit signals and defining a 32x18 DPREG configuration based on RF implementation.

Generics

wck_edge

type bit

default value ‘0’

...

type bit_vector(5 downto 0)

default value “000000”

Ports

NX_XFIFO_64x18

Description

The NX_XFIFO_64x18 provides a direct hard IP configuration for a memory based on register file elements made of 64 words of 18 bits using the NX_FIFO_U component.

Generics

wck_edge

type bit

default value ‘0’

...

type bit_vector(6 downto 0)

default value “0000000”

Ports

NX_XFIFO_32x36

Description

The NX_XFIFO_32x36 provides a direct hard IP configuration for a memory based on register file elements made of 32 words of 36 bits using the NX_FIFO_U component.

Generics

wck_edge

type bit

default value ‘0’

...

type bit_vector(6 downto 0)

default value “0000000”

Ports

NX_RFB_U

Description

Each TILE of NG-Ultra implements two Simple Dual Port memory of 32 words of 18-bit (one port is dedicated to write, the second port is dedicated to read) which can be combined to form deeper or larger memories.

...

The Impulse nxLibrary-Ultra.vhdp defines several dedicated NX IP models, instantiating NX_RFB_U component, for each of the above configurations.

...

Image Added

Figure 9: 32x18 RF implemented in a TILE of NG-Ultra

The Register_File block is made of:

...

Generics

wck_edge

type bit

default value ‘0’

...

This generic defines the desired RF configuration: 0 for DPREG, 1 for SPREG, 2 for XRF_64x18, 3 for XRF_32x36 and 4 for XRF_2R_1W.

Ports

Instantiation Example

This documentation only provides the instantiation of the component.

-- RFB 32 words of 18 bits



RFB_0 : NX_RFB_U 

generic map (

      mode => 0       –- DPREG mode selected

    , wck_edge => ‘0’ – rising edge detection for clock

    , mem_context  => "1111111111111111,0011001100110011," &

                      "1100110011001100,1111111111111111," &

                      "..."

                      -- other 64 words must be also initialized



)

port map (

      WCK => CLK

    , I1  => DI(0), ... , I16 => DI(15)

    , COR => COR, ERR => ERR

    , O1  => DO(0), ... , O16 => DO(15)

    , RA1 => RA(0), ... , RA6 => RA(5)

    , WA1 => WA(0), ... , WA6 => WA(5)

    , RE1 => OPEN,  ... , RE4 => OPEN

    , WE1 => WE

    , WE2 => OPEN,  ... , WE4 => OPEN

   );

NX_XRFB_64x18

Description

The NX_XRFB_64x18 implements a configured DPREG of 64 words of 18 bits with write clock edge configuration, using NX_RFB_U component, and providing compact vector interfaces for user convenience.

Generics

wck_edge

type bit

default value ‘0’

...

When a word size exceeds 18 bits or when the number of words exceeds 64, an error occurs.

Ports

Instantiation Example

This documentation only provides the instantiation of the component.

-- RFB 64 words of 18 bits



RFB_0 : NX_XRFB_64x18 

generic map (

      wck_edge => ‘0’

    , mem_context  => "1111111111111111,0011001100110011," &

                      "1100110011001100,1111111111111111," &

                      "..."

                      -- other 64 words must be also initialized



)

port map (

      WCK => CLK

    , I   => DI(17 downto 0)

    , O   => DO(17 downto 0)

    , RA  => RA(5 downto 0)

    , WA  => WA(5 downto 0)

    , WE  => WE

    , WEA => WEA

 );

NX_XRFB_32x36

Description

The NX_XRFB_32x36 implements a configured DPREG of 32 words of 36 bits (combining both Register files of a TILE) with write clock edge configuration, using NX_RFB_U component, and providing compact vector interfaces for user convenience.

Generics

wck_edge

type bit

default value ‘0’

...

When a word size exceeds 36 bits or when the number of words exceeds 32, an error occurs.

Ports

NX_XRFB_2R_1W

Description

The NX_XRFB_2R_1W implements a Register File configured with two read ports of 18 bits each and one write port of 18 bits with write clock edge configuration, using NX_RFB_U component, and providing compact vector interfaces for user convenience.

Generics

wck_edge

type bit

default value ‘0’

...

When a word size exceeds 18 bits or when the number of words exceeds 32, an error occurs.

Ports

NX_RFBSP_U_WRAP

Description

The NX_RFBSP_U_WRAP implements a 32x18 Register File configured with a single write/read port.

Generics

wck_edge

type bit

default value ‘0’

...

When a word size exceeds 18 bits or when the number of words exceeds 32, an error occurs.

Ports

NX_CDC_U_2DFF

Description

The NX_CDC_U_2DFF component describes a CDC (Clock Domain Crossing) module that transmits data between two clock domains CK0 and CK1. The data provided on ports A and B in source clock domain are synchronized in destination clock domain with two pipe registers.

Generics

ck0_edge

type bit

default value ‘0’

...

This generic allows to use destination reset connected to BDRSTO output when set to ‘1’.

Ports

NX_CDC_U_3DFF

Description

The NX_CDC_U_3DFF component describes a CDC (Clock Domain Crossing) module that transmits data between two clock domains CK0 and CK1. The data provided on ports A and B are registered in source clock domain with one pipe register and the synchronization of these data is done in destination clock domain with two pipe registers.

Generics

ck0_edge

type bit

default value ‘0’

...

This generic allows to use destination reset connected to BDRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

Ports

NX_CDC_U_BIN2GRAY

Description

The NX_CDC_U_BIN2GRAY component describes a hard IP that can be used before NX_CDC_U_2DFF and NX_CDC_U_3DFF clock domain crossing modules in order to translate the input data in ports A and B from binary to gray representation.

Ports

NX_CDC_U_GRAY2BIN

Description

The NX_CDC_U_GRAY2BIN component describes a hard IP that can be used before NX_CDC_U_2DFF and NX_CDC_U_3DFF clock domain crossing modules in order to translate the input data in ports A and B from gray to binary representation.

Ports

NX_XCDC_U

Description

The NX_XCDC_U component implements a fully external CDC (Clock Domain Crossing) module that transmits data between two clock domains CK1 and CK2 for 4 data ports A, B, C and D. The data provided on ports A, B, C and D are registered in source clock domain with one pipe register and the synchronization of these data is done in destination clock domain with two pipe registers.

Generics

ck0_edge

type bit

default value ‘0’

...

This generic allows to use destination reset connected to DDRSTO output when set to ‘1’ in order to reset the data destination pipe registers.

Ports

NX_DSP_U

Description

The NX_DSP_U component describes a Digital Signal Processor circuit that allows implementation of arithmetic computations such as multiply, add/subtract.

...

• CO43 output usedon NG-ULTRA instead of CO37 used on NG-LARGE

• CONCAT bloc is computed by A & B operand order instead of B & A

• Substraction is computed with 42 bits long instead of 36

• Addition can be computed on 42 bits long (but still on 36 bits too)

• Operands X and Y are inverted in ALU.

...

Figure 10: DSP simplified block diagram

...

• the reset R pin which will reset all registers (input, internal and output registers) except the cascaded output registers PR_CZ and PR_CCO.

• the reset RZ pin which will reset only the cascaded output registers PR_CZ and PR_CCO.

• the write enable WE pin which will reset all registers (input, internal and cascaded registers) except the output registers PR_Z, PR_OVF and PR_CO.

• the write enable WEZ pin which will reset only the output registers PR_Z, PR_OVF and PR_CO.

Generics

std_mode

type string

default value “”

...

...

Anchor
_Toc40370471 _Toc40370471

Anchor
_Toc99964069 _Toc99964069

Ports

Instantiation Example

This documentation only provides the instantiation of the component.

-- MUL(41:0) <= A(23:0) * B(17:0)    unsigned



signal link : std_logic_vector(35 downto 0)



DSP_0 : NX_DSP_U

generic map (

      std_mode => “UMUL_18”

)

port map (

      A1    => A(0)   , ... , A24   => A(23)

    , B1    => B(12)  , ... , B12   => B(23)

    , B13   => OPEN   , ... , B18   => OPEN

    , C1    => OPEN   , ... , C36   => OPEN

    , D1    => OPEN   , ... , D18   => OPEN

    , Z1    => OPEN   , ... , Z56   => OPEN

    , CAI1  => OPEN   , ... , CAI18 => OPEN

    , CAO1  => OPEN   , ... , CAO18 => OPEN

    , CBI1  => OPEN   , ... , CBI18 => OPEN

    , CBO1  => OPEN   , ... , CBO18 => OPEN

    , CZI1  => OPEN   , ... , CZO56 => OPEN

    , CZO1  => link(0), ... , CZO36 => link(35)

    , CZO37 => OPEN   , ... , CZO56 => OPEN    

    , CCI   => OPEN   , CCO => OPEN, CK   => OPEN

    , CI    => OPEN   , CO  => OPEN, CO43 => OPEN, CO57 => OPEN

    , OVF   => OPEN   , R   => OPEN, RZ   => OPEN, WE   => OPEN, WEZ   => OPEN

);



DSP_1 : NX_DSP_U

generic map (

      std_mode => “UMUL_EXT”

)

port map (

      A1    => A(0)   , ... , A24   => A(23)

    , B1    => B(0)   , ... , B12   => B(11)

    , B13   => OPEN   , ... , B18   => OPEN

    , C1    => OPEN   , ... , C36   => OPEN

    , D1    => OPEN   , ... , D18   => OPEN

    , Z1    => MUL(0) , ... , Z48   => MUL(47)

    , Z49   => OPEN   , ... , Z56   => OPEN

    , CAI1  => OPEN   , ... , CAI18 => OPEN

    , CAO1  => OPEN   , ... , CAO18 => OPEN

    , CBI1  => OPEN   , ... , CBI18 => OPEN

    , CBO1  => OPEN   , ... , CBO18 => OPEN

    , CZI1  => link(0), ... , CZO36 => link(35)

    , CZI36 => OPEN   , ... , CZI56 => OPEN

    , CZO1  => OPEN   , ... , CZO56 => OPEN    

    , CCI   => OPEN   , CCO => OPEN, CK   => OPEN

    , CI    => OPEN   , CO  => OPEN, CO43 => OPEN, CO57 => OPEN

    , OVF   => OPEN   , R   => OPEN, RZ   => OPEN, WE   => OPEN, WEZ   => OPEN

);

Simulation

The NX_DSP_U VHDL simulation model is included in the NxLibrary (NxPackage). It allows to simulate any one of the possible NX_DSP_U configurations.

Use Models

DSPs can be chained to create operations with greater operands.

Addition

...

Figure 11: DSP 84 bits addition

Multiplication

...

Figure 12: DSP 24x32 bits unsigned multiplication

...

Image Added

Figure 13: DSP 24x36 bits unsigned multiplication

...

Figure 14: DSP 48x36 bits unsigned multiplication

...

Image Added

Figure 15: DSP 47x35 bits signed multiplication

Multiplication and Addition

Image Added

Figure 16: DSP 24x32 bits multiplication then 56 bits addition

NX_DSP_U_SPLIT

The NX_DSP_U_SPLIT is an alternate primitive for using DSP blocks. It can be instantiated as many times as required in your design.

...

The following is the declaration of the component NX_DSP_U_SPLIT, included in the nxLibrary-Ultra.vhdp package.

component NX_DSP_U_SPLIT

generic (

-------------------------------------------------------------------------

...

-------------------------------------------------------------------------

SIGNED_MODE : bit := '0';

INV_WE : bit := '0';

INV_WEZ : bit := '0';

INV_RST: bit := '0';

INV_RSTZ : bit := '0';

ALU_DYNAMIC_OP : bit_vector(1 downto 0) := B"00"; -- '00' for Static,

-- '-1' for Dynamic control from C

-- '10' for Dynamic control from D

SATURATION_RANK : bit_vector(5 downto 0) := B"000000"; -- Weight of useful MSB on Z and CZO result

-- (to define saturation and overflow)

ENABLE_SATURATION : bit := '0'; -- '0' for Disable, '1' for Enable

MUX_CCO : bit := '0'; -- '0' for CCO = ALU(42), '1' for CCO = ALU(56)

MUX_Z : bit := '0'; -- Select Z output. '0' for Y, '1' Saturation / ALU

MUX_CZ : bit := '0'; -- Select MUX_X input. '0' for CZI, '1' for CZO

MUX_Y : bit := '0'; -- Select ALU's Y input. '0' for MULT output, '1' for (B & A)

MUX_X : bit_vector(2 downto 0) := B"000"; -- Select MUX_X operation

...

-- "110" for MUX_X >> 17

-- "111" for MUX_X >> 18

MUX_CCI : bit := '0'; -- Select '1' input of CI mux. '0' for CCI, '1' for CO_feddback

MUX_CI : bit := '0'; -- Select input carry of ALU. '0' for CI, '1' for CCI/CO_feedback mux

MUX_P : bit := '0'; -- '0' for PRE_ADDER, '0' for B input

MUX_B : bit := '0'; -- '0' = B input, '1' = CBI input

MUX_A : bit := '0'; -- '0' = A input, '1' = CAI input

PRE_ADDER_OP : bit := '0'; -- '0' = Add, '1' = Sub

-------------------------------------------------------------------------

...

-------------------------------------------------------------------------

PR_WE_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_WEZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RST_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_RSTZ_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_OV_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CO_MUX : bit := '0'; -- Registered carry out (CO42 & CO56)

PR_CCO_MUX : bit := '0'; -- Registered cascade carry out

PR_Z_MUX : bit := '0'; -- Registered output

PR_CZ_MUX : bit := '0'; -- Registered Cascade output

PR_Y_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_X_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_CI_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_MULT_MUX : bit := '0'; -- No pipe reg -- Register inside MULT

PR_P_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg (Pre-adder)

PR_D_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_C_MUX : bit := '0'; -- '0' for No pipe reg, '1' for 1 pipe reg

PR_B_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_B_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on B input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_CASCADE_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels for CAO output. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

PR_A_MUX : bit_vector(1 downto 0) := "00"; -- Number of pipe reg levels on A input. "-0" for 0 level, "01" for 1 level, "11" for 2 levels

...

-------------------------------------------------------------------------

ENABLE_PR_OV_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CCO_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Z_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CZ_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_Y_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_X_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_CI_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_MULT_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_P_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_D_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_C_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_B_RST : bit := '1'; -- '0' for Disable, '1' for Enable

ENABLE_PR_A_RST : bit := '1'; -- '0' for Disable, '1' for Enable

-- PR_CZ_INIT : bit_vector(5 downto 0) := B"000000"; -- Value of CZ's pipe register on reset

...

-------------------------------------------------------------------------

ALU_OP : bit_vector(2 downto 0) := B"000"; -- ALU operation

-- x+y+c = "000"

...

-- -x+y-c = "110"

-- -x-y+c-2 = "111"

);

port(

CK : IN std_logic;

R : IN std_logic;

RZ : IN std_logic;

WE : IN std_logic;

WEZ : IN std_logic;

CI : IN std_logic;

A : IN std_logic_vector(23 downto 0);

B : IN std_logic_vector(17 downto 0);

C : IN std_logic_vector(35 downto 0);

D : IN std_logic_vector(17 downto 0);

CAI : IN std_logic_vector(23 downto 0);

CBI : IN std_logic_vector(17 downto 0);

CZI : IN std_logic_vector(55 downto 0);

CCI : IN std_logic;

Z : out std_logic_vector(55 downto 0);

CO42 : OUT std_logic;

CO56 : OUT std_logic;

OVF : OUT std_logic;

CAO : OUT std_logic_vector(23 downto 0);

CBO : OUT std_logic_vector(17 downto 0);

CZO : OUT std_logic_vector(55 downto 0);

CCO : OUT std_logic

);

end component

NX_DSP_U_WRAP

Description

The NX_DSP_U_WRAP component provides a wrapper around NX_DSPU IP for user convenience, concatening bits into vector interfaces. The generics are the same as NX_DSP_U, check the associated section for detail explanations.

Ports

ADD84_2DSP

Description

The ADD84_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an addition between two 84-bit operands using two DSP.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Ports

SMUL47x35_4DSP

Description

The SMUL47x35_4DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer a signed multiplication between two operands of 47 and 35-bit using four DSP.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside the four DSP.

Ports

UMADD24_2DSP

Description

The UMADD_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned multiplication with addition based on a 24-bit operand and using two DSP.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Anchor
_Toc98490921 _Toc98490921

Anchor
_Toc99964091 _Toc99964091

Ports

UMUL24x32_1DSP_2CYCLES

Description

The UMUL24x32_1DSP_2CYCLES component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x32 multiplication using one DSP with cascade interface during 2 cycles.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Anchor
_Toc98490925 _Toc98490925

Anchor
_Toc99964095 _Toc99964095

Ports

UMUL24x32_2DSP

Description

The UMUL24x32_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x32 multiplication using two DSP.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Ports

UMUL24x36_1DSP_2CYCLES

Description

The UMUL24x36_1DSP_2CYCLES component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x36 multiplication using one DSP with cascade interface during 2 cycles.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Ports

UMUL24x36_2DSP

Description

The UMUL24x36_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 24x36 multiplication using two DSP.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Ports

UMUL48x36_1DSP_4CYCLES

Description

The UMUL48x36_1DSP_4CYCLES component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 48x36 multiplication using one DSP with cascade interface during 4 cycles.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Ports

UMUL48x36_4DSP

Description

The UMUL48x36_2DSP component provides a wrapper around NX_DSP_U_WRAP IP fully configured to offer an unsigned 48x36 multiplication using four DSP.

Generics

piped

type boolean

default value “true”

This generic enables by default the use of pipeline registers inside all DSP.

Ports

NX_ECC

Description

The NX_ECC component describes an Error Code Correction circuit that can be used with memory declaration to add error correction support.

...

Ports

Instantiation Example

This documentation only provides the instantiation of the component.

entity hdpecc_4Kx32 is

port(

    ckw : in std_logic;

    ckr : in std_logic;

    ckq : in std_logic;

    we  : in std_logic;

    adw : in std_logic_vector (11 downto 0);

    adr : in std_logic_vector (11 downto 0);

    di  : in std_logic_vector (31 downto 0);

    do  : out std_logic_vector (31 downto 0);

    cor : out std_logic;

    err : out std_logic

);

end entity;

architecture rtl of hdpecc_4Kx32 is 

    type mem_reg is array (4095 downto 0) of std_logic_vector(31 downto 0);

    signal mem : mem_reg;

begin

    hdpram_ecc: NX_ECC

    port map (

          CKD => ckq

        , CHK => do(0)

        , COR => cor

        , ERR => err

    );

NX_RAM

Description

The NX_RAM component describes a synchronous True Dual Port Random Access Memory circuit of 48 Kbits available in NG-MEDIUM. The circuit supports Error Code Correction (ECC, also called EDAC – Error Detection and Correction).

...

However, simultaneous write access on both ports at the same physical address, or write access simultaneous with a read access at the same physical address are not allowed.

...

Image Added

Figure 17: RAM diagram

Memory ports configurations

Optional input and output behavior and pipeline registers:

By default, the RAM block do not use pipeline registers. The output delivers a valid data T_{access_time} after the clock edge that samples the read address (ACS = ‘1’ and AWE = ‘0’) or BCS = ‘1’ and BWE = ‘0’).

...

In addition, the polarity of the block RAM clock as well as the one of the register clocks can be modified by the user (see NX_RAM raw_config0).

No ECC modes

The NO_ECC configuration mode is set by generics (raw_config1(15:12) = “0000”.

...

The figure 8 shows the physical memory organization and the dada/address lines to be used to access the array contents (output data is shown for port A only).

...

Figure 18: NX_RAM organization (No ECC)

...

As a consequence, for data write, the data input bus must be replicated one or more times on the RAM block input data pins. The following figure shows a summary for the 6 possible configurations. Only port A is shown. The rules are obviously the same for port B.

...

Figure 19: Address and data connections (No ECC)

...

• In 16K x 3 configuration, the 3-bit data input must be replicated 8 times

• In 8K x 6 configuration, the 3-bit data input must be replicated 4 times

ECC modes

When used with ECC, the user array size is restricted to 2K x 18. The 6 remaining bits of each internal address of 24-bit words are used to store the ECC signature of each 18-bit data.

...

During read cycles, the ECC decoder can detect and correct any single bit error, or detect any double bit error.

...

Figure 20: RAM organization (ECC FAST or SLOW)

...

The physical connections of address and input/output data lines is shown in the next figure.

...

Figure 21: Address and data connections (ECC FAST or SLOW)

ECC data correction in FAST mode

• If a single bit error is found, it will be automatically detected and corrected at the RAM output port. The flags ACOR or BCOR are set during the read cycle to signal the error detection and correction. However, the internal memory array remains corrupt.

• If a double bit error is detected, it can’t be corrected, and the flags AERR or BERR are asserted.

ECC data correction in SLOW mode

• This mode is also called Read Repair Mode (RRM).

• If a single bit error is found, it will be automatically detected and corrected at the RAM output port, and the memory content is automatically updated with the corrected value. The flags ACOR or BCOR are set during the user’s read cycle to signal the error detection and correction.

• If a double bit error is detected, it can’t be corrected, but the flags AERR or BERR are asserted.

• In order to correct a possible error during a read access, the read cycle becomes a read modify write, where the write half cycle is transparent to the user. For this, the NG-MEDIUM RAM blocks use a doubled internal frequency. This internal clock is generated by using an exclusive OR, between the main clock (CKA or CKB) and the 90° shifted clock (ACKD or BCKD) required to support the ECC SLOW mode.

• Using ACKD and/or BCKD in ECC SLOW mode is mandatory. It must be a 90° phase shifted version of the main clock input (ACK and/or BCK). ACKD and BCKD can each be generated with ACK and BCK by using PLL and WFGs.

• In this mode, the internal RAM block works a frequency that is double of the user’s clock. The maximum user’s clock frequency is then reduced by a factor of 2, approximately.

Generics

mcka_edge

type bit

default value ‘0’

...

• raw_config0(3 downto 0) → pipe_ia ob & pipe_ib, oa & pipe_oa, ib & pipe_obia

• raw_config1

  • FAST_2kx18 ”0011100100100100”

  • SLOW_2kx18 ”1101100100100100”

...

Extended modes for NG-ULTRA (scrubbing, test, …).

Ports

...

The BCKC and BCKD ports must be connected as described for ACKC and ACKD. BR is the synchronous reset of the optional input and output registers on port B.

Instantiation Example

-- RAM with Fast ECC: 1024 words of 18 bits and 1 read/write port



RAM_0 : NX_RAM 

generic map (

   std_mode => "FAST_2kx18",

   mem_context => (

                  "000000111111111111111111,000000001100110011001100,

                   000000110011001100110011,000000111111111111111111" &

                  "000000111111111111111111000000001100110011001100,

                   000000110011001100110011,000000111111111111111111" &

			    “...”

                  "000000111111000000111001,000000001100110011001100,

                   000000110011001100110011,000000111000111111000110" &

                  "000000111111111111111111,000000001100110011001100,

                   000000110011001100110011,000000111010110011111001" 

		   -- other 2048 words must be also initialized

   )

port map (

      ACK  => CLK,  ACKC => CLK,  ACKD => OPEN, ACKR => OPEN

    , AI1  => DI(0), ... , AI18 => DI(17)

    , AI19 => OPEN,  ... , AI24 => OPEN

    , ACOR => COR,  AERR => ERR

    , AO1  => DO(0), ... , AO18 => DO(17)

    , AO19 => OPEN,  ... , AO24 => OPEN

    , AA1  => AD(0), ... , AA10 => AD(9)

    , AA11 => OPEN,  ... , AA16 => OPEN

    , ACS  => ‘1’, AWE => WE,   AR => OPEN

    , BCK  => OPEN, BCKC => OPEN, BCKD => OPEN, BCKR => OPEN

    , BI1  => OPEN,  ... , BI24 => OPEN

    , BCOR => OPEN, BERR => OPEN

    , BO1  => OPEN,  ... , BO24 => OPEN

    , BA1  => OPEN,  ... , BA16 => OPEN

    , BCS  => OPEN, BWE => OPEN, BR => OPEN

);

Simulation

The NX_RAM VHDL simulation model is included in the NxLibrary (NxPackage.vhd). It allows to simulate any one of the possible configurations, including with ECC in FAST or SLOW modes.

NX_RAM_WRAP

Description

The NX_RAM_WRAP provides an alternate way to instantiate NX_RAM. It uses the same generics as NX_RAM, and the ports are grouped as busses whenever possible.

Generics

std_mode : string := "";

mcka_edge : bit := '0';

...

Please, refer to the NX_RAM chapter for more detailed information.

Ports

Instantiation Example