Figure 1:

List of figures

IP_SPW_BANK overview

Figure 2: SPW interface internal scheme

Figure 3: TX part waveforms

Figure 4: RX part waveforms

 Table 1:

List of tables

Acronyms

Table 2: IP SPW pads occupation

Table 3: IP generics

Table 4: IP ports

Table 5: RXO output forms

Table 6: RXO output forms

Introduction

This document is intended to help user to configure and use the Serializer/ Deserializer and Clock Recovery SpaceWire IP provided by NanoXplore (file IP_SPW_BANK.vhd).

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Note

 All All the contents of this document are protected by copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.

For any question, please contact NanoXplore team support@nanoxplore.com.

  Acronyms

Description

The IP_SPW_BANK can be instantiated for configuring SpaceWire protocol above a NG-Medium complex IO Bank.

The location of the IO Bank must be specified in the instantiation using the ‘bank’ bank generic parameter. The IP instantiates some elements in the FPGA and some in the specified bank:

•   2 WFG in FPGA

•   17 Pads in specified bank

The Figure 1 following figure represents an overview of the IP, including the two SpaceWire interfaces and the different inputs and outputs of the IP.

The input and output differential lines (DI, SI, DO, SO) are represented as an unique signal in the IP. Physically, you will have to connect 2 pads as these lines are differentials.

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The following table presents the matching between IP ports and the NG-Medium IO Bank pads locations. These locations should not be specified with the ‘addPad’ method in Python script: they are already specified inside the IP.

The following table presents the different generics to be specified in the instantiation of the IP. 

For pre synthesis simulation, only ‘dataSize’ dataSize generic is needed. Other generics are mandatory for synthesis with NXmap.

Finally, Table 4 the following table shows the signals to be connected. All the reset signals are optional, they are forced to ‘0’ by default.

The Figure 2 following figure presents a detailed view of each of the two SpaceWire interfaces included in the IP.

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When set to ‘1’, the RXRST signal can be used to stop the receiver part. It resets the synchronization between bank clock and fabric clock. It also resets the recovery clock divider to ensure a clean restart when RXRST is back to ‘0’.

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'0'.

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When set to ‘1’, the TXRST signal can be used to stop the transmitter part. It resets the synchronization between bank clock and fabric clock. It also resets the TXFCK divider to ensure a clean restart when TXRST is back to ‘0’.

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'0'.

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Waveforms

TX part

To send data, user has to use the TXI input bus starting from index 0 to index ‘dataSize-1’.

The Figure 3 following figure presents the lines of the SpaceWire when emitting a message.

The vertical red lines delimits the visible words on DO & SO outputs. LSB is sent first.

In this example, dataSize was set to 6.

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The delay between sampling of data by TXSCK (txOut on Figure 3previous figure) and serialized data on DO & SO depends on the initial conditions.

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To receive data, user has to use the RXO output bus. Depending on the dataSize set, there are one or more words available in the bus. It is important to note that the words are not aligned.

The Table 5 and Table 6 two following tables show how 6 bits long words may be organized in the RXO bus. The length of Past and Future offsets cannot be predicted.

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In most cases, the length of ‘Future’ + ‘Past’ is equal to 8 and thus there are 12 bits available for words which corresponds to 2 complete words. The repartition of the 8 bits between Past and Future parts cannot be predicted.

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For a dataSize of 6, the minimum number of bits to consider to be sure to retrieve one word is 11 bits. The Figure 4 below presents the lines of the SpaceWire when receiving a message.

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Again, the vertical red lines are just delimiting the visible words on the DI & SI lines.

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The provided example ‘SpaceWire’ is a small design which shows how to instantiate an IP_SPW_BANK IP. It includes a PLL and a WFG for the clock generation.

The generic dataSize is set to 6, and the bank generic to “IOB12” in order to use J4 & J5 SpaceWire connectors of the NG-Medium evaluation kit board v2.

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Moreover, the offset will also be different for a bitstreamed design tested on evaluation kit board. So do not worry if the switch number 1 on the board does not change the state of the led1 but of another led.