...

NX1H35AS chips are always accessible through JTAG, and also support several configuration modes. At power-up, MODE[3:0] pins state define the configuration mode. RST_N is a dedicated input pin that allows to reset the configuration engine, and launches the configuration process after RST_N is released. (It can’t be used to reset the FPGA user’s logic).

MODE[3:0]	Configuration mode
0000 0x0	RESERVED
0001 0x1	RESERVED
0010 0x2	Master Serial SPI
0011 0x3	Master Serial SPI with Vcc control
0100 0x4	Slave SpaceWire
0101 0x5	RESERVED
0110 0x6	Slave Parallel 8
0111 0x7	Slave Parallel 16

...

The next table summarizes the list of pins that can be affected during the configuration process.

Group	Name	I/O	Description
GLOBAL	MODE(3 :0)	I	Input pins sampled at power-up. MODE(3:0). They define the configuration mode to be used for NG-MEDIUM configuration. MODE(3:0) cannot be changed when RST_N = ‘1’
	CLK	I	Required only for slave parallel 8/16 configuration (20 or 50 MHz). For other configuration modes, must be tied to 3.3V via 10KOhms pullup resistor
	RST_N	I	Mandatory input. When low, it resets the internal configuration engine. RST_N must be low at least during 3 microseconds to ensure a proper configuration engine reset. When RST_N goes high, the configuration starts after up to 3 additional microseconds.
	READY	O	Goes high when the configuration is complete (the FPGA enters in user’s mode)
	ERROR	O	Generates a high level pulse (~20 ns or one CLK cycle) each time an error is encountered during the configuration.
Slave Parallel 8	CS_N	I	Active low Chip_Select input. Used in Slave Parallel 8 mode. The master can write or read to/from the configuration engine when CS_N is low during a CLK rising edge.
	WE_N	I	Active low Write_Enable input. Used in Slave Parallel 8 mode. The master can write to the configuration engine when both CS_N and WE_N are low during a CLK rising edge.
	DATA_OE	O	This pin is reserved. Must be left unconnected
	D(7 :0)	I/O	8-bit data bus used in Slave Parallel 8 mode to write the bitstream and/or read internal NG-MEDIUM internal state values

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The supported SPW instructions by the NG-Medium FPGA are as stated in table below.

Command Code	Command
0x01	ADDR_DEBUG
0x02	READ_DEBUG
0x04	WRITE_DEBUG
0x08	WRITE_CONF

...

Each byte (or word) is written on the rising edge of CLK, while CS_N and WE_N are activated (low level) simultaneously. Dummy cycles can be inserted – if required by the master by de-asserting both CS_N and WE_N during one or more cycles between any two consecutive bytes. The next figure illustrates an example of timing diagram.

Anchor

	_Figure12
	_Figure12

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Internal interface between fabric and BSM

The following signals can be used by the fabric and consequently get an impact in the design if needed by users:

Grp	Name	I/O	Description

BSM	COLD_START	I	Goes high if the FPGA is ready and not reboot because of error occurred.
	CMIC_CORR[10:0]	I	Sum of all CMIC corrected errors counters (8 bits counter by row for 5 rows).
THS	OVF	I	Overflow of allowed range.
	DRDY	I	Data is ready.
	DATA[6:0]	I	Data in the range [0;127].

Boundary scan

IEEE 1149 JTAG implementation

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NX1H35AS chips boundary scan instructions are the following:

Hex	Instruction	Function
0x0	EXTEST	Boundary scan external test
0x1	SAMPLE	Boundary scan sample
0x1	PRELOAD	Boundary scan preload
0x2	WR_CONF	Nanoxplore bitstream download
0x3	WR_DEBUG	Write debug instruction
0x4	RD_DEBUG	Read debug instruction
0x5	ADDR_DEBUG	Address debug instruction
0x6	INTEST	Boundary scan in internal test
0x7	IDCODE	Boundary scan design identification
0x8	USRCODE	User design identification register
0x9	USER1	User registers access
0xA	USER2	User registers access
0xC	HIGHZ	Tri-state all device I/Os
0xF	BYPASS	Single-clock bypass TDI to TDO

...

To access a register, the user needs to use the ADDR_DEBUG instruction first, and then the WR_DEBUG or RD_DEBUG instructions.

Address	Register Name	R/W	Description
0x00	NG-MEDIUM STATUS	R	Status register
0x0b	NG-MEDIUM JTAG_IDCODE	R	JTAG identification code
0x0c	NG-MEDIUM JTAG_USERCODE	RW	JTAG user code
0x0d	NG-MEDIUM SPI_CTRL	RW	SPI configuration
0x0e	NG-MEDIUM ERROR1	R	Error Flags
0x0f	NG-MEDIUM ERROR1_MASK	RW	Error Mask
0x10	NG-MEDIUM ERROR2	R	Error Flags
0x11	NG-MEDIUM ERROR2_MASK	RW	Error Mask
0x14	NG-MEDIUM MAX_ERROR_CNT	RW	Error counter
0x15	NG-MEDIUM DEVICE_ID	RW	FPGA Device ID
0x1a	NG-MEDIUM THSENS_CTRL	RW	Thermal Sensor Configuration
0x1b	NG-MEDIUM THSENS_DATA	R	Thermal Sensor Data
0x1c	NG-MEDIUM DUMP_CTRL	RW	DUMP configuration
0x1d	NG-MEDIUM SPW_CTRL1	RW	SPACEWIRE configuration
0x1e	NG-MEDIUM SPW_CTRL2	RW	SPACEWIRE configuration
0x1f	NG-MEDIUM LOADER_CTRL	RW	Loader Controller

STATUS

Name	Address	Access	Reset Value	Description
STATUS	0x00	Read-only	0x0000	Status register

Bits	Field name	rst	Description
[15]	had_error_unmasked	0x0	1 when ERRORx contents flags errors (without application of mask vector)
[14]	had_error	0x0	1 when ERRORx contents flags errors (with application of mask vector)
[13]	status_cmic_run	0x0	1 when CMIC is running
[5]	status_max_error	0x0	1 when the Max Error is reach
[4]	status_error	0x0	1 when the Error Flag is rise
[3]	status_download	0x0	1 when the loader download a bitstream
[2]	status_prog	0x0	1 when the Programmation Flag is rise
[1]	status_cold_start	0x0	1 when the Ready Flag is first run
[0]	status_ready	0x0	1 when the Ready Flag is rise

JTAG_IDCODE

Name	Address	Access	Reset Value	Description
JTAG_IDCODE	0x0b	Read-only	0x00000675	JTAG identification code

Bits	Field name	rst	Description
[31:28]	jtag_idcode_version	0x0	Version number
[27:12]	jtag_idcode_part	0x0	Part number
[11:1]	jtag_idcode_manufacturer	0x33a	Manufacturer ID: 11:8 (4bits) bank, 7:1 (7bits) manufacturer id
[0]	jtag_idcode_one	0x1	Constant Always 1

JTAG_USERCODE

Name	Address	Access	Reset Value	Description
JTAG_USERCODE	0x0c	Read-write	0xffffffff	JTAG user code

rst

Bits	Field name	Reset Value	Description
[31:0]	jtag_usercode	0xffffffff	JTAG user code

SPI_CTRL

Name	Address	Access	Reset Value	Description
SPI_CTRL	0x0d	Read- write	0x1f4003f	SPI configuration

Bits	Field name	rst	Description
[30:15]	spi_powerup_cycle	0x3e8	PowerUp duration (need 300us). Number of clock cycles needed for 300us
[14:12]	spi_dummy_cycle	0x0	Number of Dummy cycle
[11:4]	spi_read_code	0x3	SPI Read Code
[3:0]	spi_clk_ratio	0xf	SPI Clock frequency is divided by spi_clk_ratio+2

ERROR1

Name	Address	Access	Reset Value	Description
ERROR1	0x0e	Read-only	0x00000000	Error Flags

Bits	Field name	Description
[31]	flag_error_spi_sel	SPI selection error flag
[30]	flag_error_parallel_read_access_ovf	Parallel read access overflow
[29]	flag_error_parallel_write_access_conflict	Parallel write access conflict
[28]	flag_error_fifo_serializer_full	FIFO of serializer full
[27]	flag_error_reg_read_unaccepted	Register read access is rejected
[26]	flag_error_reg_write_unaccepted	Register write access is rejected
[25]	flag_error_bl_read_unaccepted	Bootloader read is rejected
[24]	flag_error_cfgctx_read_unaccepted	CFGCTX read is rejected
[23]	flag_error_cfgctx_write_unaccepted	CFGCTX write is rejected

Bits	Field name	Description
[22]	flag_error_clear_unaccepted	Clear command rejected
[21]	flag_error_bltest_unaccepted	Bootloader test command is rejected
[20]	flag_error_reg_read_busy	Register read busy error
[19]	flag_error_reg_write_busy	Register write busy error
[18]	flag_error_bl_read_busy	Bootloader read busy error
[17]	flag_error_cfgctx_read_busy	CFGCTX read busy error
[16]	flag_error_cfgctx_write_busy	CFGCTX write busy error
[15]	flag_error_clear_busy	Clear busy error
[14]	flag_error_bltest_busy	Bootloader test busy error
[13]	flag_error_invalid_address	Address is invalid
[12]	flag_error_direct_engine_rsp_busy	Direct engine response is busy
[11]	flag_error_direct_engine_rsp_conflict	Direct engine response in conflict
[10]	flag_error_direct_engine_req_invalid_loader	Direct engine request signals invalid loader
[9]	flag_error_access_write_conflict	Write access conflict detected
[8]	flag_error_frame_engine_edac_uncorrected	Uncorrected error on frame engine's EDAC
[7]	flag_error_frame_engine_crc_frame	CRC error detected on frame
[6]	flag_error_frame_engine_crc_bitstream	CRC error detected on bitstream
[5]	flag_error_frame_engine_watchdog_timeout	Watchdog's timeout is reached
[4]	flag_error_frame_engine_unexpected_frame	Frame received but not expected
[3]	flag_error_frame_engine_req_invalid_loader	Invalid loader error detected on frame request
[2]	flag_error_frame_access_conflict	Access conflict detected on frame
[1]	flag_error_direct_access_rsp_conflict	Direct access response conflict detected
[0]	flag_error_direct_access_req_conflict	Direct access request conflict detected

ERROR1_MASK

Name	Address	Access	Reset Value	Description
ERROR1_MASK	0x0f	Read-write	0x00000000	Error Mask

Bits	Field name	rst	Description
[31:0]	flag_error1_mask	0x0	Mask register for ERROR1

ERROR2

Name	Address	Access	Reset Value	Description
ERROR2	0x10	Read-only	0x00	Error Flags

Bits	Field name	Description
[9]	flag_error_spw_link_broken	SPW link disconnection error detected
[8]	flag_error_spw_err_int	SPW internal error detected
[7]	flag_error_spw_nom_int	SPW NOM error
[6]	flag_error_cmic_max_run	CMIC max run error
[5]	flag_error_cmic_check_uncorrected	CMIC error is uncorrected
[4]	flag_error_cmic_ref_edac_uncorrected	CMIC reference for EDAC is uncorrected
[3]	flag_error_cmic_ref_addr_ovf	CMIC reference address overflow detected
[2]	flag_error_cmic_access_conflict	Conflict detected on CMIC access
[1]	flag_error_spw_unexpected_packet	Unexpected SPW packet detected
[0]	flag_error_spw_eep	SPW EEP marker detected

ERROR2_MASK

Name	Address	Access	Reset Value	Description
ERROR2_MASK	0x11	Read-write	0x00	Error Mask

Bits	Field name	rst	Description
[9:0]	flag_error2_mask	0x0	Mask register for ERROR2

MAX_ERROR_CNT

Name	Address	Access	Reset Value	Description
MAX_ERROR_CNT	0x14	Read-write	0x0000000f	Error counter

Bits	Field name	rst	Description
[3:0]	MAX_ERROR_CNT	0xf	Maximum error count permitted before lighting error led

DEVICE_ID

Name	Address	Access	Reset Value	Description
DEVICE_ID	0x15	Read-write	0x0	FPGA Device ID

Bits	Field name	rst	Description
[3:0]	device_id	0x0	FPGA device id

THSENS_CTRL

Name	Address	Access	Reset Value	Description
THSENS_CTRL	0x1a	Read-write	0x0000	JTAG identification code

Bits

Field name

rst

Description

[15:6]

thsens_clk_ratio

0x0

Clock ratio between bitstream manager and thermal sensor

Clock frequency is divided by thsens_clk_ratio+2

[5:1]

thsens_dcorrect

0x0

Digital code to correct

[0]

thsens_power_up

0x0

Thermal Sensor is powered

THSENS_DATA

Name	Address	Access	Reset Value	Description
THSENS_DATA	0x1b	Read-only	0x00	Thermal Sensor Data

Bits	Field name	rst	Description
[8:2]	thsens_data	0x0	Thermal Sensor Ouput
[1]	thsens_overflow	0x0	Overflow of digital
[0]	thsens_enable	0x0	Thermal Sensor is online

DUMP_CTRL

Name	Address	Access	Reset Value	Description
DUMP_CTRL	0x1c	Read-write	0xf	DUMP configuration

Bits	Field name	rst	Description
[3:0]	dump_clk_ratio	0xf	DUMP Clock frequency is divided by dump_clk_ratio+2

SPW_CTRL1

Name	Address	Access	Reset Value	Description
SPW_CTRL1	0x1d	Read-write	0x0000	SPACEWIRE configuration

Bits

Field name

rst

Description

[15:8]

spw_freq_run

0x0

frequency used in run state

Clock frequency divided by (spw_freq_run+1)

[7:0]

spw_freq_init

0x0

frequency used in init state

Clock frequency divided by (spw_freq_init+1)

SPW_CTRL2

Name	Address	Access	Reset Value	Description
SPW_CTRL2	0x1e	Read-write	0x1402b	SPACEWIRE configuration

Bits

Field name

rst

Description

[17:8]

spw_delay_prg

0x140

delay of 6.4 us

Number of clock cycles needed for 6.4 us

[7:0]

spw_DisCntLim

0x2b

Disconnect time limit (850ns)

Number of clock cycles needed for 850ns

LOADER_CTRL

Name	Address	Access	Reset Value	Description
LOADER_CTRL	0x01	Read-write	0xf	Loader Controller

Bits	Field name	rst	Description
[3]	config_force	0x1	Force configuration (force bitstream load)
[2]	ready_force	0x1	Force ready flag
[1]	ready	0x1	Set ready flag when postamble frame occurs
[0]	cmic_enable	0x1	CMIC Feature Enable

...

Versions Compared

Old Version 3

New Version 4

Key

Internal interface between fabric and BSM

Boundary scan

IEEE 1149 JTAG implementation

STATUS

JTAG_IDCODE

JTAG_USERCODE

SPI_CTRL

ERROR1

ERROR1_MASK

ERROR2

ERROR2_MASK

MAX_ERROR_CNT

DEVICE_ID

THSENS_CTRL

THSENS_DATA

DUMP_CTRL

SPW_CTRL1

SPW_CTRL2

LOADER_CTRL

Page Comparison

Versions Compared

Old Version 3

New Version 4

Key

Internal interface between fabric and BSM

Boundary scan

IEEE 1149 JTAG implementation

STATUS

JTAG_IDCODE

JTAG_USERCODE

SPI_CTRL

ERROR1

ERROR1_MASK

ERROR2

ERROR2_MASK

MAX_ERROR_CNT

DEVICE_ID

THSENS_CTRL

THSENS_DATA

DUMP_CTRL

SPW_CTRL1

SPW_CTRL2

LOADER_CTRL