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[Constraint] setSite() command: compliance with LUT DFF and CY / Constraint can be set at any moment before Placing 1/5 (included)
[Constraint] constrainPath: DSP, RF, RAM and CY recognized. Distinction between Hard constrainPath (only instances in path are constrained) and Soft constrainpath (registers connected to all instances in path are constrained too).
[Constraint] reportRegisters: report the list of all registers at any step of progress
[Constraint]NxRegExp: Check Appendix “NxRegExp”
Primitive
[Primitive] NX_GCK: ‘MUX’ mode with input generated into the fabric[Primitive] NX_RAM: Support of Multi-Register Memory Read Port (case when no pipe at the output)
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[Logging] Options table for bitstreaming in logs[Logging] Added GCK to reportInstances table
Tool
[Tool] addVlogDefine command: command to override ‘Define’ in verilog file
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