Page Comparison

Features

Constraint

• [Constraint] setSite() command: compliance with LUT DFF and CY / Constraint can be set at any moment before Placing 1/5 (included)

• [Constraint] constrainPath: DSP, RF, RAM and CY recognized. Distinction between Hard constrainPath (only instances in path are constrained) and Soft constrainpath (registers connected to all instances in path are constrained too).

• [PrimitiveConstraint] NX_GCK: ‘MUX’ mode with input generated into the fabricreportRegisters: report the list of all registers at any step of progress

• [Constraint]NxRegExp: Check Appendix “NxRegExp”

• User Constrained Path Detection (small example here)

• [Reporting] https://project.nanoxplore.local/issues/1742

• [Logging] Options table for bitstreaming in logs

• [Reporting] Added GCK to reportInstances table

• [Constraint]: addBlackbox (IP): Preplacing IP and implement the routed project in the top project. All TILE and CGB instances are supported.

Primitive

• [Primitive] NX_GCK: ‘MUX’ mode with input generated into the fabric

• [Primitive] NX_RAM: Input data mapped into RAM registers Samah c’est bien ça ?

Logging

• [Logging] Options table for bitstreaming in logs

• [Logging] Added GCK to reportInstances table

• [Logging] Termination values: https://project.nanoxplore.local/issues/2103

Tool

• [Tool] DSP_U : Inferred large multiplications allowed

• [Tool] addVlogDefine command: command to override ‘Define’ in verilog file

Bug fix

Constraint

• [Constraint] IO: Wrong IO name mustn’t reserve a pad

Logging

• [Logging] Termination: TerminationReference only allowed for pads with termination

• [Logging] Multiple Emitter: Name of the signal concerned by error is reported to user

Netlist

• [Netlist] NX_IOB: generics set by addpad addPad are now passed through the macro cell

• [Netlist] NX_PLL_U: ‘use_cal’ set as integer instead of std_logic

Appendix

NxRegExp

Impacted methods:

...

 Note: