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This IP does not implement the full SpaceWire CODEC.
All All the contents of this document are protected by copyright law. They may not be disclosed to third parties or copied or duplicated in any form without the written consent of NanoXplore.
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The location of the IO Bank must be specified in the instantiation using the ‘bank’ bank generic parameter. The IP instantiates some elements in the FPGA and some in the specified bank:
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The input and output differential lines (DI, SI, DO, SO) are represented as an unique signal in the IP. Physically, you will have to connect 2 pads as these lines are differentials.
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For pre synthesis simulation, only ‘dataSize’ dataSize generic is needed. Other generics are mandatory for synthesis with NXmap.
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When set to ‘1’, the RXRST signal can be used to stop the receiver part. It resets the synchronization between bank clock and fabric clock. It also resets the recovery clock divider to ensure a clean restart when RXRST is back to ‘0’'0'.
When RXRST is set to ‘1’'1', the value on RXO output is stable but undefined. It is not set to plain zero.
When set to ‘1’, the TXRST signal can be used to stop the transmitter part. It resets the synchronization between bank clock and fabric clock. It also resets the TXFCK divider to ensure a clean restart when TXRST is back to ‘0’'0'.
When TXRST is set to ‘1’'1', the values on DO and SO outputs are forced to ‘0’'0'. The first word transmitted after a reset is undefined.
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To send data, user has to use the TXI input bus starting from index 0 to index ‘dataSize-1’.
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The vertical red lines delimits the visible words on DO & SO outputs. LSB is sent first.
In this example, dataSize was set to 6.
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The delay between sampling of data by TXSCK (txOut on previous figure) and serialized data on DO & SO depends on the initial conditions.
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To receive data, user has to use the RXO output bus. Depending on the dataSize set, there are one or more words available in the bus. It is important to note that the words are not aligned.
The two following tables show how 6 bits long words may be organized in the RXO bus. The length of Past and Future offsets cannot be predicted.
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For a dataSize of 6, the minimum number of bits to consider to be sure to retrieve one word is 11 bits. The Figure 4 below presents the lines of the SpaceWire when receiving a message.
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Again, the vertical red lines are just delimiting the visible words on the DI & SI lines.
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The provided example ‘SpaceWire’ is a small design which shows how to instantiate an IP_SPW_BANK IP. It includes a PLL and a WFG for the clock generation.
The generic dataSize is set to 6, and the bank generic to “IOB12” in order to use J4 & J5 SpaceWire connectors of the NG-Medium evaluation kit board v2.
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