Table of Content
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If mode is set to “global_lowskew”, the output signal is routed to global low skew network of fabric.
Ports
Ports | Direction | Type | Description |
I | input | std_logic | Input signal |
O | output | std_logic | Output signal |
Example
This documentation only provides the instantiation of the component.
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The blue internal signals are CMD signal sampled on rising edge (SPL1) and then sampled on falling edge (SPL0). SPL0 is the final enable.
Ports
Ports | Direction | Type | Description |
CKI | input | std_logic | Input clock |
CMD | input | std_logic | Command |
CKO | output | std_logic | Output clock |
Example
This documentation only provides the instantiation of the component.
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This generic configures the VCO frequency range. The value must be in range 0 to 2 according to the following ranges:
vco_range | VCO frequency | Unit | |
Min | Max | ||
0 | 200 | 425 | MHz |
1 | 400 | 850 | MHz |
2 | 800 | 1200 | MHz |
ref_div_on (2)
type bit
default value ‘0’
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It can be useful to maintain the input reference clock, and the VCO frequencies into their respective ranges.
ref_div_on | Reference frequency range | Unit | |
Min | Max | ||
‘0’ | 20 | 100 | MHz |
‘1’ | 40 | 200 | MHz |
ext_fbk_on (3)
type bit
default value ‘0’
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This generic allows to define (together with fbk_div_on) the division factor of the VCO frequency on the internal feedback path.
fbk_intdiv (nDivider) | fbk_div_on | Division factor on feedback path |
0 | ‘0’ | Not allowed |
1 | ‘0’ | Not allowed |
2 | ‘0’ | 4 |
3 | ‘0’ | 6 |
... | ‘0’ | ... |
30 | ‘0’ | 60 |
31 | ‘0’ | 62 |
0 | ‘1’ | Not allowed |
1 | ‘1’ | 4 |
2 | ‘1’ | 8 |
3 | ‘1’ | 12 |
... | ‘1’ | ... |
14 | ‘1’ | 56 |
15 | ‘1’ | 60 |
16 to 31 | ‘1’ | Not allowed |
clk_outdiv1 (8)
type integer (range 0 to 7)
...
The calibration procedure takes about 10 µs at startup. No status is available on NG-MEDIUM.
Ports
Ports | Direction | Type | Description |
REF | In | std_logic | Reference clock input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled. |
FBK | In | std_logic | External FeedBack input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) |
VCO | Out | std_logic | VCO output : Fvco = fbk_intdiv * 2**(fbk_div_on - ref_div_on + 1) * clk_ref_freq Connectivity: WFG inputs |
D1…D3 | Out | std_logic | Divided clocks. Fvco frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128 Important note: D1, D2 and D3 outputs are reset while PLL RDY is not asserted. Connectivity: WFG inputs |
OSC | Out | std_logic | Internal 200 MHz oscilator Connectivity :WFG inputs, delay calibration system |
RDY | Out | std_logic | High when PLL is locked Connectivity: RDY inputs of WFGs, fabric… |
Instantiation Example
This documentation only provides the instantiation of the component.
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REF: input reference clock. The input reference clock enters in the REF pin. (20MHz to 50MHz max)
FBK: The feedback can be external (via clock tree connected to the FBK pin) for phase controlled outputs, or internal to the PLL (no phase control or adjustment of the generated clocks with the REF pin).
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The REFerence frequency can be divided by factors ranging from 1 to 32 be fore reaching the VCO input. This allows to give more flexibility of the PLL generated output frequency, and increase the PLL input frequency range.
ref_intdiv value | Vco input frequency | REF frequency range |
0 | Fref | 20 to 50 MHz |
1 | Fref / 2 | 40 to 100 MHz |
2 | Fref / 3 | 60 to 150 MHz |
3 | Fref / 4 | 80 to 200 MHz |
29 | Fref / 30 | |
30 | Fref / 31 | |
31 | Fref / 32 |
ref_osc_on
type bit
default value ‘0’
...
type Integer range 0 to 31
default value 2
fbk_intdiv | Division factor on internal feedback path |
0 | 4 |
1 | 6 |
2 | 8 |
3 | 10 |
... | ... |
30 | 64 |
31 | 66 |
fbk_delay_on
type bit
default value ‘0’
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The calibration procedure takes about 10 µs at startup. The “CAL_LOCKED” output goes high when the delay calibration process is complete. Can be used as status bit.
Ports
Ports | Direction | Type | Description |
REF | In | std_logic | Reference clock input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) Note: If REF pin is connected to a PAD, please declare the pad with Turbo mode enabled. |
FBK | In | std_logic | External FeedBack input Connectivity: semi-dedicated clock inputs, clock trees (low skew network) |
R | In | std_logic | Active high Reset input. Must be activated when REF input frequency changes to force a re-locking process of the PLL |
VCO | Out | std_logic | VCO output: - Internal feedback: Fvco = 2 * (fbk_intdiv + 2) * clk_ref_freq / (ref_intdiv + 1) - External feedback: Fvco = (pattern_end + 1) / n_sim_pat * clk_ref_freq / (ref_intdiv + 1) Where n_sim_pat is the number of similar patterns sequence found in pattern_end+1 MSB bits of pattern. |
REFO | Out | std_logic | Output of the REFerence divider. The division factor is set by the generic “ref_intdiv” |
LDFO | Out | std_logic | Output of the FBK_INTDIV divider. The division factor is set by the generic ‘fbk_intdiv” |
DIVP1 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp1” |
DIVP2 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp2” |
DIVP3 | Out | std_logic | This output delivers a divided VCO frequency (by a power of 2). The division factor is set by the generic “clk_divoutp3o2” |
DIVO1 | Out | std_logic | This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divouto1” |
DIVO2 | Out | std_logic | This output delivers a divided VCO frequency (by an odd factor). The division factor is set by the generic “clk_divoutp3o2” |
OSC | Out | std_logic | 200 MHz coming from 400MHz internal oscilator Connectivity :WFG inputs, delay calibration engine |
PLL_LOCKED | Out | std_logic | High when PLL is locked Connectivity: RDY inputs of WFGs, fabric… |
CAL_LOCKED | Out | std_logic | High when the automatic calibration procedure of the current FPGA quarte area is complete Connectivity: fabric |
Instantiation Example
This documentation only provides the instantiation of the component.
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This generic configures whether the input clock is inverted (‘1’) or not (‘0’). When sampling the input clock, this generic configures whether the sampling is done on rising edge (‘0’) or falling edge (‘1’).
Ports
Ports | Direction | Type | Description |
SI | input | std_logic | Synchronization input (connected to the synchronization output of the master WFG) |
ZI | input | std_logic | Input clock (connected to PLL VCO or D1, D2 or D3 output) |
RDY | input | std_logic | Usually connected to the PLL RDY pin. Must be left unconnected for the WFG that generates the clock feedback for the PLL using external feedback. RDY input is an active low reset. When low, it disables the WFG behavior. When high or open, the WFG works as specified. |
SO | output | std_logic | Synchronization output (Master WFG SO output is connected to all slave WFGs SI inputs) |
ZO | output | std_logic | Generated clock (connected to clock tree) |
Synchronizing WFG together can be useful if output clocks must be synchronous. It is made by getting the same source clock for Master and Slave WFG and connecting SO from Master WFG to Si of Slave WFG.
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This generic configures whether the input clock is inverted (‘1’) or not (‘0’). When sampling the input clock, this generic configures whether the sampling is done on rising edge (‘0’) or falling edge (‘1’).
Ports
Ports | Direction | Type | Description |
SI | input | std_logic | Synchronization input (connected to the synchronization output of the master WFG) |
ZI | input | std_logic | Input clock (connected to PLL VCO or D1, D2 or D3 output) |
RDY | input | std_logic | Usually connected to the PLL RDY pin. Must be left unconnected for the WFG that generates the clock feedback for the PLL using external feedback. RDY input is an active low reset. When low, it disables the WFG behavior. When high or open, the WFG works as specified. |
R | Input | std_logic | Active high Reset. Can be fed by the LOCKED output of the NX_PLL_L. |
SO | output | std_logic | Synchronization output (Master WFG SO output is connected to all slave WFGs SI inputs) |
ZO | output | std_logic | Generated clock (connected to clock tree) |
Synchronizing WFG together can be useful if output clocks must be synchronous. It is made by getting the same source clock for Master and Slave WFG and connecting SO from Master WFG to Si of Slave WFG.
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This generic represents the way the CI (carry in) port is connected: 0 is for low, 1 for high and 2 for propagate which means it is connected to the previous NX_CY CO (carry out) port.
Ports
Ports | Direction | Type | Description |
A[1:4] | input | std_logic | A input of each stage |
BI[1:4] | input | std_logic | B input of each stage |
CI | input | std_logic | Carry input |
CO | output | std_logic | Carry output |
S[1:4] | output | std_logic | Output of each stage |
Example
This documentation only provides the instantiation of the component..
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This generic represents the truth table of the associated LUT. The string representing the truth table is MSB ordered (“b(15), b(14),...b(1), b(0)”) and b(15) to b(0) are defined as in the following table:
I4 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
I3 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
I2 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
I1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
O | b(15) | b(14) | b(13) | b(12) | b(11) | b(10) | b(9) | b(8) | b(7) | b(6) | b(5) | b(4) | b(3) | b(2) | b(1) | b(0) |
Lut_table examples for common 4-input functions:
I4 and I3 and I2 and I1 => lut_table = b“1000000000000000” (or x”8000”)
I4 or I3 or I2 or I1 => lut_table = b“1111111111111110” (or x”FFFE”)
(I4 and I3) xor (I2 and I1) => lut_table = x”0111 1000 1000 1000” (or x”7888”)
Ports
Ports | Direction | Type | Description |
I[1:4] | input | std_logic | LUT inputs |
O | output | std_logic | Output |
Example
This documentation only provides the instantiation of the component.
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| Note |
|---|
Only dff_type = 0 is allowed for NG-MEDIUM and NG-LARGE. |
Ports
Ports | Direction | Type | Description |
I | input | std_logic | Input |
CK | input | std_logic | Clock |
L | input | std_logic | Load |
R | input | std_logic | Reset |
O | output | std_logic | Output |
Example
This documentation only provides the instantiation of the component.
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This generic represents the front polarity of the WCK clock. ‘0’ is for rising edge and ‘1’ for falling edge.
Ports
Ports | Direction | Type | Description |
RCK | input | std_logic | Read clock |
WCK | input | std_logic | Write clock |
I[1:16] | input | std_logic | Data input |
COR | output | std_logic | Correction output flag |
ERR | output | std_logic | Error output |
O1 to O16 | output | std_logic | Data output |
RA1 to RA6 | input | std_logic | Read address |
RE1 to RE4 | input | std_logic | Read enable |
WA1 to WA6 | input | std_logic | Write address |
WE1 to WE4 | input | std_logic | Write enable |
Instantiation Example
This documentation only provides the instantiation of the component.
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This generic configures the following fields:
Name | Index | Description |
CO_SEL | 19 | Carry out MUX for CO and CCO outputs ‘0’ : Select CO37 ‘1’ : Select CO49 |
ALU_DYNAMIC_OP | 18 | ALU Dynamic Operation ‘0’: use raw_config3 as ALU operation ‘1’: use D1…D6 as ALU operation |
SATURATION_RANK | 17:12 | MSB position for saturation and overflow Signed : “100000” for range -2**31 to (2**31)-1 Unsigned : “100000” for range 0 to (2**32)-1 Max value = “110111” (55) |
ENABLE_SATURATION | 11 | ‘0’: disable, ‘1’: enable |
Z_FEEDBACK_SHL12 | 10 | Shift of the Z output for feedback ‘0’ : No shift ‘1’ : 12-bit left shift |
MUX_Z | 9 | Selection for Z output ‘0’ : ALU ‘1’ : PR_Y |
MUX_CI | 8 | Carry in MUX ‘0’ : CI input ‘1’ : CCI cascade input |
MUX_Y | 7 | Y operand MUX ‘0’ : MULT ‘1’ : Concat (B, A) |
MUX_X | 6:5 | X operand MUX “00” : C (sign extended to 56-bit) “01” : CZI “11” : CZI(43:0] & C(11:0] “10” : Z (12-bit left shifted or not) |
MUX_P | 4 | Pre-adder/ B MUX (to multiplier) ‘0’ : B (sign extended) ‘1’ : Pre-adder |
MUX_B | 3 | B input MUX ‘0’ : Select B input port ‘1’ : Select CBI input |
MUX_A | 2 | A input MUX. ‘0’ : Select A input port ‘1’ : Select CAI input |
PRE_ADDER_OP | 1 | Pre-adder operation ‘0’ : add (performs B+D) ‘1’ : subtract (performs B-D) |
SIGNED_MODE | 0 | ‘0’ : unsigned, ‘1’: signed |
raw_config1
type bit_vector(21 downto 0)
...
This generic configures the following fields:
Name | Index | Description |
RESERVED | 21:19 | “000” |
PR_OV_MUX | 18 | ALU overflow pipe register ‘0’ : no pipeline ‘1’ : pipeline |
PR_CO_MUX | 17 | Carry out pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_Z_MUX | 16 | Z output pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_ALU_MUX | 15 | ALU out pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_MUL_MUX | 14 | Multiplier out pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_Y_MUX | 13 | Y operand pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_X_MUX | 12 | X operand pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_P_MUX | 11 | Pre-adder pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_CI_MUX | 10 | Carry in pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_D_MUX | 9 | D input pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_C_MUX | 8 | C input pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_B_CAS_MUX | 7:6 | Cascaded B input pipe depth B input pipe depth Cascaded A input pipe depth A input pipe depth “00” : no pipeline “01” : 1 level pipeline register “10” : 2 levels pipeline “11” : 3 levels pipeline |
PR_B_MUX | 5:4 | |
PR_A_CAS_MUX | 3:2 | |
PR_A_MUX | 1:0 |
raw_config2
type bit_vector(12 downto 0)
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This generic configures the following fields:
Name | Index | Description |
PR_OV_RST | 12 | ALU overflow pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_CYO_RST | 11 | Carry out pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_Z_RST | 10 | Z output pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_ALU_RST | 9 | ALU out pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_MUL_RST | 8 | Multiplier out pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_Y_RST | 7 | Y operand pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_X_RST | 6 | X operand pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_P_RST | 5 | Pre-adder pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_CYI_RST | 4 | Carry in pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_D_RST | 3 | D input pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_C_RST | 2 | C input pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_B_RST | 1 | B input pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_A_RST | 0 | A input pipe reset (‘0’ : disable, ‘1’ : enable) |
raw_config3
type bit_vector(6 downto 0)
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This generic configures the following fields:
Name | Index | Description |
ALU_MUX | 6 | Swap ALU operand (‘0’ : no swap, ‘1’ : swap) |
ALU_OP | 5:0 | ALU operation (16 valid values over 64 possible combinations) |
ALU operation must be set based on the following table:
Operation | Opcode | Equation |
|---|---|---|
Arithmetic operation | ||
ADD | b”000000” | Z = Y + X |
ADDC | b”000001” | Z = Y + X + CI |
SUB | b”001010” | Z = Y – X |
SUBC | b”001011” | Z = Y – X – CI |
INCY | b”000101” | Z = Y + CI |
DECY | b”000111” | Z = Y – CI |
Logic operation | ||
Y | b”100000” | Z = Y |
notY | b”110000” | Z = ~Y |
AND | b”100001” | Z = Y & X |
ANDnotX | b”101001” | Z = Y & ~X |
NAND | b”110001” | Z = ~(Y & X) |
OR | b”100010” | Z = Y | X |
ORnotX | b”101010” | Z = Y | ~X |
NOR | b”110010” | Z = ~(Y | X) |
XOR | b”100011” | Z = Y ^ X |
XNOR | b”110011” | Z = ~(Y ^ X) |
INVALID OP | 48 other possible values | Z = XXXXXXXXXXXXXX |
Ports
Ports | Direction | Type | Description |
A1 to A24 | input | std_logic | 24-bit A input |
B1 to B18 | input | std_logic | 18-bit B input |
C1 to C36 | input | std_logic | 36-bit C input |
CAI1 to CAI18 | input | std_logic | 18-bit Cascaded A input |
CAO1 to CAO18 | output | std_logic | 18-bit Cascaded A output |
CBI1to CBI18 | input | std_logic | 18-bit Cascaded B input |
CBO1 to CBO18 | output | std_logic | 18-bit Cascaded B output |
CCI | input | std_logic | Cascaded Carry input |
CCO | output | std_logic | Cascaded Carry output |
CI | input | std_logic | Carry input |
CK | input | std_logic | Clock (works on rising edges) |
CO | output | std_logic | Carry output |
CO37 | output | std_logic | Carry output bit 37 |
CO49 | output | std_logic | Carry output bit 49 |
CZI1 to CZI56 | input | std_logic | 56-bit Cascaded Z input |
CZO1 to CZO56 | output | std_logic | 56-bit Cascaded Z output |
D1 to D18 | input | std_logic | 18-bit D input |
OVF | output | std_logic | Overflow output flag |
R | input | std_logic | Reset for pipeline registers except Z output register (active high) |
RZ | input | std_logic | Reset for Z output register only(active high) |
WE | input | std_logic | Write enable: ‘0’: all DSP internal registers are frozen, ‘1’: normal operation |
Z1 to Z56 | output | std_logic | 56-bit Z output |
Instantiation Example
This documentation only provides the instantiation of the component.
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This generic configures the following fields:
Name | Index | Description |
CO_SEL | 19 | Carry out MUX for CO and CCO outputs ‘0’ : Select CO37 ‘1’ : Select CO49 |
ALU_DYNAMIC_OP | 18 | ALU Dynamic Operation ‘0’: use raw_config3 as ALU operation ‘1’: use D1…D6 as ALU operation |
SATURATION_RANK | 17:12 | MSB position for saturation and overflow Signed : “100000” for range -2**31 to (2**31)-1 Unsigned : “100000” for range 0 to (2**32)-1 Max value = “110111” (55) |
ENABLE_SATURATION | 11 | ‘0’: disable, ‘1’: enable |
Z_FEEDBACK_SHL12 | 10 | Shift of the Z output for feedback ‘0’ : No shift ‘1’ : 12-bit left shift |
MUX_Z | 9 | Selection for Z output ‘0’ : ALU ‘1’ : PR_Y |
MUX_CI | 8 | Carry in MUX ‘0’ : CI input ‘1’ : CCI cascade input |
MUX_Y | 7 | Y operand MUX ‘0’ : MULT ‘1’ : Concat (B, A) |
MUX_X | 6:5 | X operand MUX “00” : C (sign extended to 56-bit) “01” : CZI “11” : CZI(43:0] & C(11:0] “10” : Z (12-bit left shifted or not) |
MUX_P | 4 | Pre-adder/ B MUX (to multiplier) ‘0’ : B (sign extended) ‘1’ : Pre-adder |
MUX_B | 3 | B input MUX ‘0’ : Select B input port ‘1’ : Select CBI input |
MUX_A | 2 | A input MUX. ‘0’ : Select A input port ‘1’ : Select CAI input |
PRE_ADDER_OP | 1 | Pre-adder operation ‘0’ : add (performs B + D) ‘1’ : subtract (performs B - D) |
SIGNED_MODE | 0 | ‘0’ : unsigned, ‘1’: signed |
raw_config1
type bit_vector(21 downto 0)
...
This generic configures the following fields:
Name | Index | Description |
RESERVED | 21:19 | “000” |
PR_OV_MUX | 18 | ALU overflow pipe register ‘0’ : no pipeline ‘1’ : pipeline |
PR_CO_MUX | 17 | Carry out pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_Z_MUX | 16 | Z output pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_ALU_MUX | 15 | ALU out pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_MUL_MUX | 14 | Multiplier out pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_Y_MUX | 13 | Y operand pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_X_MUX | 12 | X operand pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_P_MUX | 11 | Pre-adder pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_CI_MUX | 10 | Carry in pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_D_MUX | 9 | D input pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_C_MUX | 8 | C input pipe depth ‘0’ : no pipeline ‘1’ : pipeline |
PR_B_CAS_MUX | 7:6 | Cascaded B input pipe depth B input pipe depth Cascaded A input pipe depth A input pipe depth “00” : no pipeline “01” : 1 level pipeline register “10” : 2 levels pipeline “11” : 3 levels pipeline |
PR_B_MUX | 5:4 | |
PR_A_CAS_MUX | 3:2 | |
PR_A_MUX | 1:0 |
raw_config2
type bit_vector(12 downto 0)
...
This generic configures the following fields:
Name | Index | Description |
PR_OV_RST | 12 | ALU overflow pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_CYO_RST | 11 | Carry out pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_Z_RST | 10 | Z output pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_ALU_RST | 9 | ALU out pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_MUL_RST | 8 | Multiplier out pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_Y_RST | 7 | Y operand pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_X_RST | 6 | X operand pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_P_RST | 5 | Pre-adder pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_CYI_RST | 4 | Carry in pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_D_RST | 3 | D input pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_C_RST | 2 | C input pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_B_RST | 1 | B input pipe reset (‘0’ : disable, ‘1’ : enable) |
PR_A_RST | 0 | A input pipe reset (‘0’ : disable, ‘1’ : enable) |
raw_config3
type bit_vector(6 downto 0)
...
This generic configures the following fields:
Name | Index | Description |
ALU_MUX | 6 | Swap ALU operand (‘0’ : no swap, ‘1’ : swap) |
ALU_OP | 5:0 | ALU operation (16 valid values over 64 possible combinations) |
ALU operation must be set based on the following table:
Operation | Opcode | Equation |
|---|---|---|
Arithmetic operation | ||
ADD | b”000000” | Z = Y+ X |
ADDC | b”000001” | Z = Y + X + CI |
SUB | b”001010” | Z = Y – X |
SUBC | b”001011” | Z = Y – X – CI |
INCY | b”000101” | Z = Y + CI |
DECY | b”000111” | Z = Y – CI |
Logic operation | ||
Y | b”100000” | Z = Y |
NotY | b”110000” | Z = ~Y |
AND | b”100001” | Z = Y & X |
ANDnotX | b”101001” | Z = Y & ~X |
NAND | b”110001” | Z = ~(Y & X) |
OR | b”100010” | Z = Y | X |
ORnotX | b”101010” | Z = Y | ~X |
NOR | b”110010” | Z = ~(Y | X) |
XOR | b”100011” | Z = Y ^ X |
XNOR | b”110011” | Z = ~(Y ^ X) |
INVALID OP | 48 other possible values | Z = XXXXXXXXXXXXXX |
Ports
Ports | Direction | Type | Description |
A1 to A24 | input | std_logic | 24-bit A input |
B1 to B18 | input | std_logic | 18-bit B input |
C1 to C36 | input | std_logic | 36-bit C input |
CAI1 to CAI23 | input | std_logic | 24-bit Cascaded A input |
CAO1 to CAO24 | output | std_logic | 24-bit Cascaded A output |
CBI1to CBI18 | input | std_logic | 18-bit Cascaded B input |
CBO1 to CBO18 | output | std_logic | 18-bit Cascaded B output |
CCI | input | std_logic | Cascaded Carry input |
CCO | output | std_logic | Cascaded Carry output |
CI | input | std_logic | Carry input |
CK | input | std_logic | Clock (works on rising edges) |
CO | output | std_logic | Carry output |
CO37 | output | std_logic | Carry output bit 37 |
CO57 | output | std_logic | Carry output bit 57 |
CZI1 to CZI56 | input | std_logic | 56-bit Cascaded Z input |
CZO1 to CZO56 | output | std_logic | 56-bit Cascaded Z output |
D1 to D18 | input | std_logic | 18-bit D input |
OVF | output | std_logic | Overflow output flag |
R | input | std_logic | Reset for pipeline registers except Z output register (active high) |
RZ | input | std_logic | Reset for Z output register only(active high) |
WE | input | std_logic | Write enable: ‘0’: all DSP internal registers are frozen, ‘1’: normal operation |
Z1 to Z56 | output | std_logic | 56-bit Z output |
Instantiation Example
This documentation only provides the instantiation of the component.
...
| Note |
|---|
COR and ERR flags are not initialized leading to unpredictable state before 1st reading. |
Ports
Ports | Direction | Type | Description |
CKD | input | std_logic | Input clock |
CHK | input | std_logic | Check link This pin must be connected to the LSB of the output memory block – for each port requiring the ECC function. |
COR | output | std_logic | One error found and corrected |
ERR | output | std_logic | Errors found and not corrected |
Instantiation Example
This documentation only provides the instantiation of the component.
...
The possible configuration ratios on each port can be defined either with the “std_mode” or the “raw_config1 generic. Among the available NX_RAM configurations :
“std_mode” values | NG-MEDIUM “raw_config1” equivalent | NG-LARGE “raw_config1” equivalent | ||
NO ECC | Ports width | NO ECC | Ports width | |
"NOECC_48kx1" | 0000 000 000 000 000 | 0000 000 000 000 000 | ||
"NOECC_24kx2" | 0000 001 001 001 001 | 0000 001 001 001 001 | ||
"NOECC_12kx4" | 0000 010 010 010 010 | 0000 010 010 010 010 | ||
"NOECC_6kx8" | 0000 011 011 011 011 | 0000 011 011 011 011 | ||
"NOECC_4kx12" | 0000 100 100 100 100 | 0000 100 100 100 100 | ||
"NOECC_2kx24" | 0000 101 101 101 101 | 0000 101 101 101 101 | ||
"NOECC_16kx3" | Not allowed | 0000 110 110 110 110 | ||
"NOECC_8kx6" | Not allowed | 0000 111 111 111 111 | ||
In addition, the user can define several different NX_RAM configurations by directly assigning the “raw_config1” generic value, and assign the optional input and output pipeline registers with “raw_config0” generic.
...
This generic configures the optional pipeline registers on input and outputs of A and B ports:
Name | Index | Description |
PB_OUT_PR_MUX | 3 | Port B output optional pipeline register. ‘0’: no register ‘1’: Pipe register is used |
PA_OUT_PR_MUX | 2 | Port A output optional pipeline register. ‘0’: no register ‘1’: Pipe register is used |
PB_IN_PR_MUX | 1 | Port B input optional pipeline register. ‘0’: no register ‘1’: Pipe register is used |
PA_IN_PR_MUX | 0 | Port A input optional pipeline register. ‘0’: no register ‘1’: Pipe register is used |
raw_config1
type bit_vector(15 downto 0)
...
This generic configures the following fields:
Name | Index | Description |
PB_ECC_RRM | 15 | ECC Read Repair Mode on port B |
PA_ECC_RRM | 14 | ECC Read Repair Mode on port A |
PX_ECC_FAST | 13 | Fast mode ECC. Must be low if PB_ECC_RRM and PA_ECC_RRM are set to ‘1’ |
PX_ECC | 12 | Enable ECC |
PB_OUT_WIDTH | 11:9 | B port output width |
PA_OUT_WIDTH | 8:6 | A port output width |
PB_IN_WIDTH | 5:3 | B port input width |
PA_IN_WIDTH | 2:0 | A port input width |
Input / output widths values depend on PX_ECC:
...
The bits raw_config1(15 downto 12) are used to define the NO_ECC, ECC_FAST or ECC_SLOW modes. The following table shows the possible configuration values.
15 | 14 | 13 | 12 | Comment |
0 | 0 | 0 | 0 | Normal mode (NO ECC) |
0 | 0 | 0 | 1 | Invalid configuration |
0 | 0 | 1 | 0 | Invalid configuration |
0 | 0 | 1 | 1 | ECC FAST mode (no read repair) |
0 | 1 | 0 | 0 | Invalid configuration |
0 | 1 | 0 | 1 | ECC SLOW (read repair enabled on port A) |
0 | 1 | 1 | 0 | Invalid configuration |
0 | 1 | 1 | 1 | Invalid configuration |
1 | 0 | 0 | 0 | Invalid configuration |
1 | 0 | 0 | 1 | ECC SLOW (read repair enabled on port B) |
1 | 0 | 1 | 0 | Invalid configuration |
1 | 0 | 1 | 1 | Invalid configuration |
1 | 1 | 0 | 0 | Invalid configuration |
1 | 1 | 0 | 1 | ECC SLOW (read repair enabled on both ports) |
1 | 1 | 1 | 0 | Invalid configuration |
1 | 1 | 1 | 1 | Invalid configuration |
raw_l_enable
type bit
default value b’0’
...
This generic is reserved for future versions.
Ports
Ports | Direction | Type | Description |
|---|---|---|---|
ACK | input | std_logic | A port memory main clock |
ACKC | input | std_logic | A port memory clock clone. Must be connected to the same clock source as ACK |
ACKD | input | std_logic | A port memory 90° shifted clock. ACKD must be used when Read Repair Mode is selected on this port. It allows to internally generate a double frequency for the memory matrix, to allow read modify write during a single user’s clock cycle. |
ACKR | input | std_logic | A port register clock. ACKR must be fed by a valid clock (typically ACK), if the optional input or output pipeline registers are used. |
BCK | input | std_logic | B port memory main clock. |
BCKC | input | std_logic | B port memory clock clone. Same comments as for ACKC |
BCKD | input | std_logic | B port memory 90° shifted clock. Just as ACKD, BCKD is used when Read Repair Mode is selected on B port. |
BCKR | input | std_logic | B port register clock. BCKR must be fed by a valid clock (typically BCK), if the optional input or output pipeline registers are used. |
AI1 to AI24 | input | std_logic | A port input data. See notes on data input width for proper operation. |
BI1 to BI24 | input | std_logic | B port input data. See notes on data input width for proper operation. |
ACOR | output | std_logic | Goes high for one clock cycle when an error has been detected and corrected on port A |
AERR | output | std_logic | Goes high for one clock cycle when an uncorrectable error has been found on port A |
BCOR | output | std_logic | Goes high for one clock cycle when an error has been detected and corrected on port A |
BERR | output | std_logic | Goes high for one clock cycle when an uncorrectable error has been found on port A |
AO1 to AO24 | output | std_logic | A port output data. See notes on data output width for proper operation |
BO1 to BO24 | output | std_logic | B port output data. See notes on data output width for proper operation |
AA1 to AA16 | input | std_logic | A port address. See notes on physical and logical addresses for proper operation |
ACS | input | std_logic | A port chip select (active high) |
AWE | input | std_logic | A port write enable (active high) |
AR | input | std_logic | A port registers reset (active high) |
BA1 to BA16 | input | std_logic | B port address. See notes on physical and logical addresses for proper operation |
BCS | input | std_logic | B port chip select (active high) |
BWE | input | std_logic | B port write enable (active high) |
BR | input | std_logic | B port registers reset (active high) |
The ACKC port must be connected and is a clone of the memory clock (ACK).
...
Please, refer to the NX_RAM chapter for more detailed information.
Ports
Ports | Direction | Type | Description |
ACK | input | std_logic | A port memory main clock |
ACKD | input | std_logic | A port memory 90° shifted clock. ACKD must be used when Read Repair Mode is selected on this port. It allows to internally generate a double frequency for the memory matrix, to allow read modify write during a single user’s clock cycle. |
ACKR | input | std_logic | A port register clock. ACKR must be fed by a valid clock (typically ACK), if the optional input or output pipeline registers are used. |
BCK | input | std_logic | B port memory main clock. |
BCKD | input | std_logic | B port memory 90° shifted clock. Just as ACKD, BCKD is used when Read Repair Mode is selected on B port. |
BCKR | input | std_logic | B port register clock. BCKR must be fed by a valid clock (typically BCK), if the optional input or output pipeline registers are used. |
AI(23:0) | input | std_logic_vector | A port input data. See notes on data input width for proper operation. |
BI(23:0) | input | std_logic_vector | B port input data. See notes on data input width for proper operation. |
ACOR | output | std_logic | Goes high for one clock cycle when an error has been detected and corrected on port A |
AERR | output | std_logic | Goes high for one clock cycle when an uncorrectable error has been found on port A |
BCOR | output | std_logic | Goes high for one clock cycle when an error has been detected and corrected on port A |
BERR | output | std_logic | Goes high for one clock cycle when an uncorrectable error has been found on port A |
AO(23:0) | output | std_logic_vector | A port output data. See notes on data output width for proper operation |
BO(23:0) | output | std_logic_vector | B port output data. See notes on data output width for proper operation |
AA(15:0) | input | std_logic_vector | A port address. See notes on physical and logical addresses for proper operation |
ACS | input | std_logic | A port chip select (active high) |
AWE | input | std_logic | A port write enable (active high) |
AR | input | std_logic | A port registers reset (active high) |
BA(15:0) | input | std_logic_vector | B port address. See notes on physical and logical addresses for proper operation |
BCS | input | std_logic | B port chip select (active high) |
BWE | input | std_logic | B port write enable (active high) |
BR | input | std_logic | B port registers reset (active high) |
Instantiation Example
| Code Block | ||
|---|---|---|
| ||
-- RAM with Fast ECC: 1024 words of 18 bits and 1 read/write port
RAM_0 : NX_RAM
generic map (
std_mode => "FAST_2kx18",
mem_context => (
"000000111111111111111111,000000001100110011001100,
000000110011001100110011,000000111111111111111111" &
"000000111111111111111111000000001100110011001100,
000000110011001100110011,000000111111111111111111" &
“...”
"000000111111000000111001,000000001100110011001100,
000000110011001100110011,000000111000111111000110" &
"000000111111111111111111,000000001100110011001100,
000000110011001100110011,000000111010110011111001"
-- other 2048 words must be also initialized
)
port map (
ACK => CLK, ACKC => CLK, ACKD => OPEN, ACKR => OPEN
, AI1 => DI(0), ... , AI18 => DI(17)
, AI19 => OPEN, ... , AI24 => OPEN
, ACOR => COR, AERR => ERR
, AO1 => DO(0), ... , AO18 => DO(17)
, AO19 => OPEN, ... , AO24 => OPEN
, AA1 => AD(0), ... , AA10 => AD(9)
, AA11 => OPEN, ... , AA16 => OPEN
, ACS => ‘1’, AWE => WE, AR => OPEN
, BCK => OPEN, BCKC => OPEN, BCKD => OPEN, BCKR => OPEN
, BI1 => OPEN, ... , BI24 => OPEN
, BCOR => OPEN, BERR => OPEN
, BO1 => OPEN, ... , BO24 => OPEN
, BA1 => OPEN, ... , BA16 => OPEN
, BCS => OPEN, BWE => OPEN, BR => OPEN
); |
...
location => ”IOB12_D4P”,
locked => ‘1’,
Ports
Ports | Direction | Type | Description |
I | Input | std_logic | From FPGA fabric |
C | Input | std_logic | Tristate control ‘0’: High impedance ‘1’: Enable output |
T | Input | std_logic | Termination control ‘0’: No calibration ‘1’: calibration activated |
O | output | std_logic | To FPGA fabric |
IO | inout | std_logic | External pad |
Example
This documentation only provides the instantiation of the component.
...
location => ”IOB12_D4P”,
locked => ‘1’,
Ports
Ports | Direction | Type | Description |
C | Input | Std_logic | Not used. Must be left “open” or unconnected |
T | Input | std_logic | Termination control ‘0’ : No termination ‘1’ : Input termination activated |
O | output | std_logic | From FPGA fabric |
IO | Input | std_logic | External pad |
Example
This documentation only provides the instantiation of the component.
...
location => ”IOB12_D4P”,
locked => ‘1’,
Ports
Ports | Direction | Type | Description |
I | input | std_logic | From FPGA fabric |
C | input | std_logic | Tristate control (‘0’ for High Z) |
T | input | std_logic | Not used. Must be left “open” or unconnected |
IO | output | std_logic | External pad |
Example
This documentation only provides the instantiation of the component.
...
DCK : delay registers clock (can be asynchronous with SCK/FCK). Usually 2 to 20 MHz. Write operations occur on DCK rising edge.
DID(4:0) : address identifier of the considered I/O in the complex bank (0 to 29).
DRA(4:0) : address of the I/O in the considered complex bank (0 to 29). Note that when DRA = DID, the DRO outputs, as well as FLD and FLG flags outputs of the considered I/O go to low impedance (allowing thus to be read by the fabric).
DS(1:0) : allow to select the destination register into the DRA selected I/O. See next table for details.
DS value | Selected delay register |
00 | Output (and tri-state control) delay register |
01 | Input delay register |
10 | DPA delay register |
11 | Reserved |
DRI(5:0) :value to be written into the selected register.
DRL : active high load (write enable)
...
inputSignalSlope => ”8”
Ports
Ports | Direction | Type | Description |
FCK | In | Std_logic | Fast clock (bit clock) |
SCK | In | Std_logic | Slow clock (word clock) |
R | In | Std_logic | Active high Reset |
IO | In | Std_logic | Input pad |
O | Out | Std_logic_vector (data_size-1 downto 0) | Sampled word to FPGA fabric |
DCK | In | Std_logic | Delay lines management registers clock |
DRL | In | Std_logic | Delay Registers Load |
DIG | In | Std_logic | ‘0’ for Multicast write (*) ‘1’ for normal operation |
DS | In | Std_logic_vector (1 downto 0) | Delay Select : 00 => out & tri-state regs 01 => input delay register 10 => DPA delay register 11 => RESERVED |
DRA | In | Std_logic_vector (4 downto 0) | Delay address (0 to 29) |
DRI | In | Std_logic_vector (5 downto 0) | Data input to delay registers |
DRO | Out (with tri-state) | Std_logic_vector (5 downto 0) | Delay value being read Active when DRA = DID else high impedance |
DID | Out | Std_logic_vector (4 downto 0) | Pad address identification |
FZ | In | Std_logic | Active low Flags Reset |
FLD | Out (with tri-state) | Std_logic | Early capture flag Active when DRA = DID else high impedance |
FLG | Out (with tri-state) | Std_logic | Late capture flag Active when DRA = DID else high impedance |
(*) : When DIG is low, any write cycle will write the same value into all corresponding registers – selected by DS(1:0) - of the 30 I/Os in the current complex I/O bank.
...
outpuCapacity => “15“
Ports
Ports | Direction | Type | Description |
FCK | In | Std_logic | Fast clock (bit clock) |
SCK | In | Std_logic | Slow clock (word clock) |
R | In | Std_logic | Active high Reset |
IO | Out | Std_logic | Input pad |
I | In | Std_logic_vector (data_size-1 downto 0) | Data to be serialized from fabric |
DCK | In | Std_logic | Delay lines management registers clock |
DRL | In | Std_logic | Delay Registers Load |
DS | In | Std_logic_vector (1 downto 0) | Delay Select : 00 => out & tri-state regs 01 => input delay register 10 => DPA delay register 11 => RESERVED |
DRA | In | Std_logic_vector (4 downto 0) | Delay address (0 to 29) |
DRI | In | Std_logic_vector (5 downto 0) | Data input to delay registers |
DRO | Out (with tri-state) | Std_logic_vector (5 downto 0) | Delay value being read Active when DRA = DID, else high-impedance) |
DID | Out | Std_logic_vector (4 downto 0) | Pad address identifier (0 to 29 |
Reserved
There are some other components defined in NX library that are reserved for post synthesis and post place & route simulation. These components cannot be instantiated in pre synthesis VHDL.
...