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Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation | |
addADCLocation | X | ||||||
addBank |
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addBanks |
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addBlackBox |
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addDACLocation | X | ||||||
addFalsePath |
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addFile | X |
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addFiles | X |
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addHSSLLocation | |||||||
addIP | X |
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addMappingDirective |
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addMaxDelayPath |
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addMemoryInitialization |
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addMinDelayPath |
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addModule |
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addMulticyclePath |
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addObstruction | X | ||||||
addPLLLocation |
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addPad |
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addPads |
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addParameter | X |
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addParameters | X |
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addPin |
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addPins |
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addRegion | X | ||||||
addRingLocation |
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addRingLocations |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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importSdcFile |
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clearBanks |
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clearFabricPrePlaceConstraints | X | ||||||
clearPLLs |
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clearPads |
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clearPins |
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clearWFGs |
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confineModule |
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constrainModule |
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constrainPath |
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createAnalyzer |
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createClock |
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createGeneratedClock |
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createSimulator |
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destroy (project) | X |
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destroy (analyzer) | X | ||||||
developCKGs |
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exportAsIPCore | X |
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exportPlacement | X | ||||||
exportRegions | X |
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exportSites | X |
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generateBitstream |
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generateSTANetlist | X |
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getAnalyzer | X | ||||||
getDirectory | X |
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getErrorCount | X | ||||||
getHierInfo | X | ||||||
getLowskewSignals | X |
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getProject | X | ||||||
getRemarkCount | X | ||||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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getWarningCount | X | ||||||
importPlacement | X | ||||||
initRegister |
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injectLowskew | X | ||||||
listAvailableLocations | X |
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load | X |
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modifyAperture | X | ||||||
modifyObstruction | X | ||||||
modifyPad | X | ||||||
modifyRegion |
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place | X |
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progress | X |
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printError | X | ||||||
printHierInfo | X | ||||||
printRemark | X | ||||||
PrintText | X | ||||||
PrintWarning | X | ||||||
rejectLowskew | X |
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removeFile | X |
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removeFiles | X |
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removeObstruction | X | ||||||
removeRegion | X | ||||||
removeSoftModules | X | ||||||
reportDesignComplexity | X | ||||||
reportHierarchyComplexity | X | ||||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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setCaseAnalysis |
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setClockGroup |
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setDescription | X |
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setDeviceID |
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setDirectory | X |
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setFalsePath |
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setFocus |
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setGCKCount |
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setInputDelay |
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setMaxDelay |
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setMinDelay |
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setMulticyclePath |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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setSite |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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...
| Code Block | ||||
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project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'),getRegister('data_reg[0]'), 'clk1_div2', {'DivideBy': 2}) |
destroy() (project)
This method is used to destroy the project.
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| Code Block |
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Display after destruction
Traceback (most recent call last):
File "test.py", line 22, in <module>
project.display()
impulse.error: Invalid Request: Obsolete object |
destroy() (analyzer)
This method is used to destroy the analyzer.
This method takes no argument.
Example:
| Code Block | ||
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a = project.createAnalyzer()
a.launch()
a.destroy() |
display()
This method is used to open current project in impulse graphic user interface. It can be called several times from the same Python script.
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| Code Block | ||
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simulator.addWaves([‘A’, ‘B’, ‘O’]) |
destroy()
This method is used to destroy the simulator object.
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