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Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation | |||
addADCLocation | X | ||||||||
addBank |
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addBanks |
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addBlackBox |
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addDACLocation | X | ||||||||
addFalsePath |
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addFile | X |
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addFiles | X |
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addHSSLLocation | |||||||||
addIP | X |
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addMappingDirective |
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addMaxDelayPath |
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addMemoryInitialization |
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addMinDelayPath |
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addModule |
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addMulticyclePath |
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addObstruction | X | ||||||||
addPLLLocation |
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addPad |
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addPads |
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addParameter | X |
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addParameters | X |
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addPin |
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addPins |
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addRegion | X | ||||||||
addRingLocation |
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addRingLocations |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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importSdcFile |
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clearBanks |
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clearFabricPrePlaceConstraints | X | ||||||||
clearPLLs |
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clearPads |
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clearPins |
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clearWFGs |
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confineModule |
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constrainModule |
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constrainPath |
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createAnalyzer |
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createClock |
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createGeneratedClock |
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createSimulator |
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destroy | X |
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developCKGs |
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exportAsIPCore | X |
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exportPlacement | X | ||||||||
exportRegions | X |
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exportSites | X |
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generateBitstream |
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generateSTANetlist | X |
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getAnalyzer | X | ||||||||
getDirectory | X |
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getErrorCount | X | ||||||||
getHierInfo | X | ||||||||
getLowskewSignals | X |
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getProject | X | ||||||||
getRemarkCount | X | ||||||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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getWarningCount | X | ||||||||
importPlacement | X | ||||||||
initRegister |
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| listAvailableLocations | X |
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load | X |
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modifyAperture | X | ||||||||
modifyObstruction | X | ||||||||
modifyPad | X | ||||||||
modifyRegion |
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place | X |
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progress | X |
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printError | X | ||||||||
printHierInfo | X | ||||||||
printRemark | X | ||||||||
PrintText | X | ||||||||
PrintWarning | X | ||||||||
rejectLowskew | X |
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removeFile | X |
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removeFiles | X |
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removeObstruction | X | ||||||||
removeRegion | X | ||||||||
removeSoftModules | X | ||||||||
reportDesignComplexity | X | ||||||||
reportHierarchyComplexity | X | ||||||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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setCaseAnalysis |
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setClockGroup |
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setDescription | X |
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setDeviceID |
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setDirectory | X |
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setFalsePath |
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setFocus |
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setGCKCount |
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setInputDelay |
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setMaxDelay |
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setMinDelay |
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setMulticyclePath |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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setSite |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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...
| Code Block |
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project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.initRegister('SPI_CTRL', '0x01f4003f')
project.generateBitstream('bitstream.nxb') |
...
injectLowskew(signal, [lobes])
This method is used to limit inject a lowskew signal to be used in only signal in lowskew network in specified lobes.
Arguments:
Name | Type | Description |
signal | string | name of the signal. |
lobes | string | list of specified allowed lobes for the lowskew signals. Lobes must be separated by “,” character |
Example:
| Code Block |
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project.injectLowskew('clk') project.limitLowskewinjectLowskew('clk_right','Rx1,Rx2,Rx3,Rx4') |
...