...
Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation |
addADCLocation | X | |||||
addBank |
|
|
| X |
|
|
addBanks |
|
|
| X |
|
|
addBlackBox |
| X |
|
|
|
|
addDACLocation | X | |||||
addFalsePath |
|
|
|
| X | X |
addFile | X |
|
|
|
|
|
addFiles | X |
|
|
|
|
|
addHSSLLocation | ||||||
addIP | X |
|
|
|
|
|
addMappingDirective |
| X |
|
|
|
|
addMaxDelayPath |
|
|
|
| X | X |
addMemoryInitialization |
|
|
| X |
|
|
addMinDelayPath |
|
|
|
| X | X |
addModule |
| X |
|
|
|
|
addMulticyclePath |
|
|
|
| X | X |
addObstruction | X | |||||
addPLLLocation |
|
| X |
|
|
|
addPad |
| X | X |
|
|
|
addPads |
| X | X |
|
|
|
addParameter | X |
|
|
|
|
|
addParameters | X |
|
|
|
|
|
addPin |
| X | X |
|
|
|
addPins |
| X | X |
|
|
|
addRegion | X | |||||
addRingLocation |
|
| X |
|
|
|
addRingLocations |
|
| X |
|
|
|
addVerilogIncludeDirectories | X |
|
|
|
|
|
addVerilogIncludeDirectory | X |
|
|
|
|
|
addVlogDefine | X |
|
|
|
|
|
addVlogDefines | X |
|
|
|
|
|
addWFGLocation |
|
| X |
|
|
|
applySdcFileimportSdcFile |
|
|
| X |
| |
clearBanks |
| X |
|
|
| |
clearFabricPrePlaceConstraints | X | |||||
clearPLLs |
| X |
|
|
| |
clearPads |
| X |
|
|
| |
clearPins |
| X |
|
|
| |
clearWFGs |
| X |
|
|
| |
confineModule |
|
| X |
|
|
|
constrainModule |
| X | X |
|
|
|
constrainPath |
| X | X |
|
|
|
createAnalyzer |
|
|
|
| X |
|
createClock |
|
|
|
| X |
|
createGeneratedClock |
|
|
|
| X |
|
createSimulator |
|
|
|
|
| X |
destroy | X |
|
|
|
|
|
developCKGs |
|
|
|
| X |
|
exportAsIPCore | X |
|
|
|
|
|
exportPlacement | X | |||||
exportRegions | X |
|
|
|
|
|
exportSites | X |
|
|
|
|
|
generateBitstream |
|
|
| X |
|
|
generateSTANetlist | X |
|
|
|
|
|
getAnalyzer | X | |||||
getDirectory | X |
|
|
|
|
|
getErrorCount | X | |||||
getHierInfo | X | |||||
getLowskewSignals | X |
|
|
|
|
|
getProject | X | |||||
getRemarkCount | X | |||||
getTimingUnit | X |
|
|
|
|
|
getTopCellName | X |
|
|
|
|
|
getVariantName | X |
|
|
|
|
|
getWarningCount | X | |||||
importPlacement | X | |||||
initRegister |
|
|
| X |
|
|
limitLowskew |
|
| X |
|
|
|
listAvailableLocations | X |
|
|
|
|
|
load | X |
|
|
|
|
|
modifyAperture | X | |||||
modifyObstruction | X | |||||
modifyPad | X | |||||
modifyRegion |
|
| X |
|
|
|
place | X |
|
|
|
|
|
progress | X |
|
|
|
|
|
printError | X | |||||
printHierInfo | X | |||||
printRemark | X | |||||
PrintText | X | |||||
PrintWarning | X | |||||
rejectLowskew | X |
| X |
|
|
|
removeFile | X |
|
|
|
|
|
removeFiles | X |
|
|
|
|
|
removeObstruction | X | |||||
removeRegion | X | |||||
removeSoftModules | X | |||||
reportDesignComplexity | X | |||||
reportHierarchyComplexity | X | |||||
reportInstances | X |
|
|
|
|
|
reportLowskewSignals | X |
|
|
|
|
|
reportPorts | X |
|
|
|
|
|
reportRegions | X |
|
|
|
|
|
reportRegisters | X |
|
|
|
|
|
resetTimingConstraints | X |
|
|
|
|
|
route | X |
|
|
|
|
|
save | X |
|
|
|
|
|
setAnalysisConditions |
|
|
|
| X |
|
setCaseAnalysis |
|
|
|
| X |
|
setClockGroup |
|
|
|
| X |
|
setDescription | X |
|
|
|
|
|
setDeviceID |
|
|
| X |
|
|
setDirectory | X |
|
|
|
|
|
setFalsePath |
|
|
|
| X |
|
setFocus |
|
| X |
|
|
|
setGCKCount |
|
| X |
|
|
|
setInputDelay |
|
|
|
| X |
|
setMaxDelay |
|
|
|
| X |
|
setMinDelay |
|
|
|
| X |
|
setMulticyclePath |
|
|
|
| X |
|
setOption | X |
|
|
|
|
|
setOptions | X |
|
|
|
|
|
setOutputDelay |
|
|
|
| X |
|
setSite |
|
| X |
|
|
|
setTopCellName | X |
|
|
|
|
|
setVariantName | X |
|
|
|
|
|
synthesize | X |
|
|
|
|
|
...
| Code Block | ||
|---|---|---|
| ||
project.addWFGLocation('wfg_0', 'CKG2.WFG_M3) |
...
importSdcFile(filePath)
This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.
...
| Code Block | ||
|---|---|---|
| ||
project.applySdcFileimportSdcFile(./sdc_directory/constraints.sdc) |
...