...
Type | Mapping targets |
ADD | LUT, CY, DSP |
LTN | LUT, CY, DSP |
MUL | CY,DSP |
RAM | DFF, RF, RAM, RAM_ECC, DFFRAM_ECC_SLOW |
ROM | LUT, RF, RAM, RAM_ECC, RAM_ECC_SLOW |
Instance name must match the following pattern: ‘PATHNAME|INSTANCENAME’
| Note |
|---|
RAM_ECC_SLOW is not only available for NG-MEDIUM/NG-LARGE |
Example:
If the HDL design named myTest contains a small 3 write ports and 3 read ports FIFO named myFifo, nxpython cannot automatically map it into RF or RAM, but user can add a mapping directive to map it into DFF:
...
The following table shows the revision history of the Impulse_NXpython specification document:
ra_Date | Version | Revision |
2022-12-15 | 1.0.1 | Initial draft datasheet. |