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This document is intended to guide users on NXmap Impulse software best practice.
The aim is to ease NXmap Impulse using and get the best recommendations in order to implement a project into NanoXplore components.
For any kind of helpassistance, please contact NanoXplore support team at support@nanoxplore.com.
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NanoXplore FPGAs contain a low-skew network in order to spread signal with high fanout like clock, reset , and load signals.
The user must be very careful about the way to spread clock through the design. It is advised to follow the following rules sorted by level of recommendation:
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PLL outputs are connected to WFG of the same CKG. User can either instantiate a WFG or let the tool instantiate a WFG in bypass mode by itself. WFG outputs are connected to the low-skew network. |
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There are some signals with high fan out fanout can be mapped into low-skew network and introduced some important delays. It could be the problem with synchronous signals load, set, reset, …
In order to avoid this problemissue, use rejectLowskew method.
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In addition, when a LUT is used, the DFF from the same Functionnal Element will be used either as a register or a buffer so adding pipeline in the design won’t will not consume any additional instance.
Project creation
NXmap Impulse is based on Python scripts that is to say consider a project is as a class and all options and constraints are methods associated to this class.
The user can either create a project based on a NanoXplore template (recommended) or start it from scratch.
In case of To use a NanoXplore template, please ask NanoXplore support team at support@nanoxplore.com.
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Never add a nxLibrary file to your project. NXmap Impulse tool already get the needed files with NX primitives. |
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If reported messages are not clear enough to solve the issue, contact the NanoXplore support team at support@nanoxplore.com giving the CONTEXT code and an archive in order to reproduce the issue (RTL sources + scripts).
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After errors and warnings are solved or understood, check hierarchy.rpt and progress.rpt in order to check the number of instances if it is relevant with the estimation.
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Once the project is mature enough, Static Timing Analysis can be done in order to check how fast the design can operatesoperate.
STA tool can be launched from any step after Preparing (Placing 1/5) with the following example method:
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It is advised to launch a STA after Preparing as it shows up most critical paths and the maximum frequency with most optimistic hypothesis. If maximum frequencies are not higher enough at this step, it won’t the value will be less after routing for sure.
Clock creation
The input clock frequencies and other parameters must be informed to NXmap Impulse for STA.
Please refer to createClock and createGeneratedClock described in Impulse 23.3 NxPython Specification .
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It is possible to map this operators in LUT, Carry or DSP thanks to using addMappingDirective method described in Impulse 23.3 NxPython Specification .
By default, adders are mapped into Carry and Multipliers in DSP. But it can sometimes be interesting to change modify default mapping directives.
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Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction thanks to using addMappingDirective method described in Impulse 23.3 NxPython Specification .
By default, small memories (equal or less than 64x16) will be mapped into RF and bigger ones mapped into RAM. But it can sometimes be interesting to change modify default mapping directives.
It it is highly recommended to size the design according to available depths and heights. Otherwise, too many memories will be instantiated and will affect the routing and STA performances.
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In order to improve the maximum clock frequency for each clock domain, it is advised to follow the following steps:
Define a floor plan floorplan for the design depending on module relationships and pinout.
Apply the floor plan floorplan to your NXmap Impulse project using confineModule described in Impulse 23.3 NxPython Specification . Check #Floor_planning_Constrain_module for information about constraint setting.
If needed, repeat this process going deeper and deeper in the design hierarchy.
For last most critical paths, use constrainPath described in Impulse 23.3 NxPython Specification in order to create a region with only a few elements contained into the specified path. Check #Floor_planning_Constrain_path_between_registers for information about constraint setting.
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It is also possible to place manually instances in a specified spot thanks to using the following NXpython methods all described in Impulse 23.3 NxPython Specification :
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08:50:49:info | -------------------------------------------- 08:50:49:info | - Detailed Hierarchy Statistics - 08:50:49:info | -------------------------------------------- 08:50:49:info | ~ hierarchical 08:50:49:info | Resources: 08:50:49:info | NX_LUT : 13 08:50:49:info | NX_DFF : 73 08:50:49:info | NX_IOB : 51 08:50:49:info | NX_BFR : 99 08:50:49:info | NX_WFG : 3 08:50:49:info | ~ |-> row_col_pipe(X212B9C19) [ GEN_HIER0 ] 08:50:49:info | |-> Resources: 08:50:49:info | |-> NX_LUT : 3 08:50:49:info | |-> NX_DFF : 23 08:50:49:info | GEN_HIER0_ROW-0 | |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[0].ROW_PIPE ] 08:50:49:info | | |-> Resources: 08:50:49:info | | |-> NX_DFF : 5 08:50:49:info | ~ | |-> timing_pipe(X2A98C8C6) [ GEN_HIER0|GEN_ROW[1].ROW_PIPE ] 08:50:49:info | | |-> Resources: 08:50:49:info | | |-> NX_DFF : 5 |
How to use NXpython
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constraints methods
Mapping directive
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developCKGs method is active by default, NXmap compute Impulse computes automatically PLL and WFG required frequencies if input clock is declared.
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The higher the number of iterations is, the higher STA performances can be high but the higher . However, higher is the runtime is.
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All clocks must be created before launching Place&Route with TimingDriven option. Otherwise, the tool does not get performances to reach. |
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First of all, ConstrainModule methods method as explained in #Floor_planning_Constrain_module must be applied in order to concentrate parts of the design and place them close to other ones if there are interconnections between them.
In addition, ConstraintPath methods method as explained in #Floor_planning_Constrain_path_between_registers must be applied if some path paths go trough multiple modules or for last critical paths.
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With this solution, the user must pay attention to interconnections between modules and between module and output interfacesmodules and the ring device. |
Logic depth reducing
The highest the required frequency is, the lowest the number of combinatorial elements between 2 registers must be.
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