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The user can then reuse the result of this first flow in another design. named top, which instanciates the IP entity several times.

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To specify that an entity of the design top must be taken into account as a preplaced IP, the user has to add the following constraint before the synthesis

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nxpython reports user modules detection in the hierarchy.rpt (previous figure) file with detailed information including resources used for each module and detailed hierarchy of all modules defined in the current project.

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In the example above, to define a clock with 100MHz for net "Clk", the following three commands are equivalent:

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In the example above, the master clock "Clk" was created as 100MHz and the generated clock "clk1" is divided by 2 from the master clock. But noted that the "clk_reg" is driven by falling edge of master clock, the relation between the master clock and generated clock is the following:

project = createProject()
project.load('routed.nym')
project.createClock(getPort('Clk'), 'Clk', 10000)
or
project.createGeneratedClock(getRegisterClock('clk_reg'),getRegisterClock('reg2'), 'clk1', {'DivideBy': 2})
or
project.createGeneratedClock(getClock('Clk'),getRegisterClock('reg2'), 'clk1', {'Edges': [2, 4, 6]})

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createSimulator()

This method is used to create a simulator object. A simulator object is used to simulate the project with a specified testbench.

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project = createProject()
project.load('/home/user/example/vhdl/simple/native.nym')
options = { ‘coreName’: ‘IPCore’, ‘encrypt’: ‘All’ }
p.exportAsIPCore(‘IPCore.vhd’, options)
p.synthesize()

exportPlacement([filename])

This method is used to export all placement constraints in order to be re-imported.

Example:

project.exportPlacement()

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The output HTML file looks like:

 reportHierarchyComplexity()

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reportLowskewSignals(logfile)

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reportLowskewSignals(logfile)

This method reports the lowskew signals:

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resetTimingConstraints()

This method is used to reset all timing constraints for current project.

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Clock skew

Clock skew is the difference between the latch clock delay at the destination register and launch clock delay at the source register. Considering the example shown in previous figure, clock skew is calculated as follows:

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Data arrival time

In impulse, data arrival time includes the overall data delay, clock skew and setup/hold time (recovery/removal) for a critical timing path in a domain. Based on the setup/hold verification, data arrival time can be either maximum or minimum. In both cases, data arrival time is calculated as follows:

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Case 2

If launch and latch clocks have active high and active low edges respectively, in this case hold relationship is established between active high launch edge and the previous active low latch edge with the minimum difference. Similarly, setup relationship is established between launch edge and the next latch edge with the minimum difference.

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Case 3

For the active low launch clock and active high latch clock, the hold relationship gives the minimum delay between active low launch edge and previous active high latch edge. Similarly, setup relationship gives the minimum delay between the active low launch edge and the very next active high latch edge as shown in the following figure.

Case 4

If both launch and latch clocks have active low edges, the hold relationship is established between active low launch edge and previous active low latch edge. Similarly, setup relationship is established between the active low launch edge and the very next active low latch edge as shown in the following figure.

Slack calculation

In impulse, setup/recovery slack corresponds to the difference between maximum setup/recovery relationship and maximum data arrival time whereas hold/removal slack corresponds to the difference between minimum data arrival and minimum hold/removal relationship.

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Path detail

Following the critical paths table, all the listed critical paths are reported in detail. For each part of the path, the table contents the following information: source (beginning of the path), target (ending of the path), routing delay, internal delay, cumulated delay (from the source of the path), setup/recovery time (for data path), hold/removal time (for data path), clock skew (for data path).

Revision history

The following table shows the revision history of the Impulse_NXpython specification document:

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