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Méthod | Project | Synthesize | Place & Route | Bitstream | STA | Simulation |
addADCLocation | X | |||||
addBank |
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| X |
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addBanks |
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| X |
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addBlackBox |
| X |
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addDACLocation | X | |||||
addFalsePath |
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| X | X |
addFile | X |
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addFiles | X |
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addHSSLLocation | ||||||
addIP | X |
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addMappingDirective |
| X |
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addMaxDelayPath |
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| X | X |
addMemoryInitialization |
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| X |
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addMinDelayPath |
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| X | X |
addModule |
| X |
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addMulticyclePath |
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| X | X |
addObstruction | X | |||||
addPLLLocation |
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| X |
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addPad |
| X | X |
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addPads |
| X | X |
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addParameter | X |
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addParameters | X |
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addPin |
| X | X |
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addPins |
| X | X |
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addRegion | X | |||||
addRingLocation |
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| X |
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addRingLocations |
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| X |
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addVerilogIncludeDirectories | X |
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addVerilogIncludeDirectory | X |
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addVlogDefine | X |
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addVlogDefines | X |
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addWFGLocation |
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| X |
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applySdcFile |
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| X |
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clearBanks |
| X |
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clearFabricPrePlaceConstraints | X | |||||
clearPLLs |
| X |
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clearPads |
| X |
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clearPins |
| X |
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clearWFGs |
| X |
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confineModule |
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| X |
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constrainModule |
| X | X |
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constrainPath |
| X | X |
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createAnalyzer |
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| X |
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createClock |
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| X |
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createGeneratedClock |
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| X |
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createSimulator |
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| X |
destroy | X |
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developCKGs |
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| X |
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exportAsIPCore | X |
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exportPlacement | X | |||||
exportRegions | X |
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exportSites | X |
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generateBitstream |
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| X |
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generateSTANetlist | X |
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getAnalyzer | X | |||||
getDirectory | X |
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getErrorCount | X | |||||
getHierInfo | X | |||||
getLowskewSignals | X |
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getProject | X | |||||
getRemarkCount | X | |||||
getTimingUnit | X |
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getTopCellName | X |
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getVariantName | X |
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getWarningCount | X | |||||
importPlacement | X | |||||
initRegister |
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| X |
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limitLowskew |
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| X |
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listAvailableLocations | X |
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load | X |
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modifyAperture | X | |||||
modifyObstruction | X | |||||
modifyPad | X | |||||
modifyRegion |
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| X |
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place | X |
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progress | X |
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printError | X | |||||
printHierInfo | X | |||||
printRemark | X | |||||
PrintText | X | |||||
PrintWarning | X | |||||
rejectLowskew | X |
| X |
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removeFile | X |
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removeFiles | X |
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removeObstruction | X | |||||
removeRegion | X | |||||
removeSoftModules | X | |||||
reportDesignComplexity | X | |||||
reportHierarchyComplexity | X | |||||
reportInstances | X |
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reportLowskewSignals | X |
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reportPorts | X |
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reportRegions | X |
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reportRegisters | X |
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resetTimingConstraints | X |
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route | X |
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save | X |
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setAnalysisConditions |
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| X |
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setCaseAnalysis |
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| X |
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setClockGroup |
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| X |
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setDescription | X |
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setDeviceID |
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| X |
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setDirectory | X |
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setFalsePath |
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| X |
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setFocus |
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| X |
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setGCKCount |
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| X |
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setInputDelay |
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| X |
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setMaxDelay |
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| X |
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setMinDelay |
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| X |
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setMulticyclePath |
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| X |
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setOption | X |
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setOptions | X |
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setOutputDelay |
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| X |
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setSite |
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| X |
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setTopCellName | X |
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setVariantName | X |
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synthesize | X |
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This section presents the methods related to the project object.
addADCLocation(name, location)
This method is used to place an ADC in a specific location
Example:
Name | Type | Description |
name | string | the name of the instance. The path must be set entirely. |
location | string | the spot in which to set the instance. |
Example:
| Code Block | ||
|---|---|---|
| ||
project.addADCLocation('WRAPPER_0|ADC_0','ADC1') |
addBank(name, dict)
The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.
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Among the instances of the ring, some are not supported yet :PLL, WFG, CR5, SOC_IF, HSSL
addDACLocation(name, location)
This method is used to place a DAC in a specific location
Example:
Name | Type | Description |
name | string | the name of the instance. The path must be set entirely. |
location | string | the spot in which to set the instance. |
Example:
| Code Block | ||
|---|---|---|
| ||
project.addDACLocation('WRAPPER_0|DAC_0','DAC1') |
addFalsePath(from_list, to_list)
...