Page Comparison

...

Heraafter a table of all available nxpython commands and the context they affect:

Méthod	Project	Synthesize	Place & Route	Bitstream	STA	Simulation
addBank				X
addBanks				X
addBlackBox		X
addFalsePath					X	X
addFile	X
addFiles	X
addHSSLLocation
addIP	X
addMappingDirective		X
addMaxDelayPath					X	X
addMemoryInitialization				X
addMinDelayPath					X	X
addModule		X
addMulticyclePath					X	X
addObstruction			X
addPLLLocation			X
addPad		X	X
addPads		X	X
addParameter	X
addParameters	X
addPin		X	X
addPins		X	X
addRegion			X
addRingLocation			X
addRingLocations			X
addVerilogIncludeDirectories	X
addVerilogIncludeDirectory	X
addVlogDefine	X
addVlogDefines	X
addWFGLocation			X
applySdcFile					X
clearBanks			X
clearFabricPrePlaceConstraints			X
clearPLLs			X
clearPads			X
clearPins			X
clearWFGs			X
confineModule			X
constrainModule		X	X
constrainPath		X	X
createAnalyzer					X
createClock					X
createGeneratedClock					X
createSimulator						X
destroy	X
developCKGs					X
exportAsIPCore	X
exportPlacement	X
exportRegions	X
exportSites	X
generateBitstream				X
generateSTANetlist	X
getAnalyzer	X
getDirectory	X
getErrorCount	X
getHierInfo	X
getLowskewSignals	X
getProject	X
getRemarkCount	X
getTimingUnit	X
getTopCellName	X
getVariantName	X
getWarningCount	X
importPlacement	X
initRegister				X
limitLowskew			X
listAvailableLocations	X
load	X
modifyAperture			X
modifyObstruction			X
modifyPad	X
modifyRegion			X
place	X
progress	X
printError	X
printHierInfo	X
printRemark	X
PrintText	X
PrintWarning	X
rejectLowskew	X		X
removeFile	X
removeFiles	X
removeObstruction			X
removeRegion			X
removeSoftModules		X
reportDesignComplexity	X
reportHierarchyComplexity	X
reportInstances	X
reportLowskewSignals	X
reportPorts	X
reportRegions	X
reportRegisters	X
resetTimingConstraints	X
route	X
save	X
setAnalysisConditions					X
setCaseAnalysis					X
setClockGroup					X
setDescription	X
setDeviceID				X
setDirectory	X
setFalsePath					X
setFocus			X
setGCKCount			X
setInputDelay					X
setMaxDelay					X
setMinDelay					X
setMulticyclePath					X
setOption	X
setOptions	X
setOutputDelay					X
setSite			X
setTopCellName	X
setVariantName	X
synthesize	X

General commands

This chapter presents the general purpose commands. These commands do not need any object to be called as they are directly defined in the impulse module.

...

This method is used to create an empty project object. The project can then be loaded or built.

Arguments:

Name	Type	Description
workingDirectory	string	the working directory in which files will be saved

When no argument is supplied, the working directory will be the one nxpython is launched from.

...

When using this method, the global number of errors is incremented by 1.

Arguments:

Name	Type	Description
message	string	error message to print

Example:

Code Block

language	py

printError("It's a trap!")

...

When using this method, the global number of remarks is incremented by 1.

Arguments:

Name	Type	Description
message	string	remark message to print

Example:

Code Block
printRemark("This is a remark")

...

This function is used to print a message in the impulse output. This includes terminal output and log file if set. When no message is given, method prints a new line in the impulse output.

Arguments:

Name	Type	Description
message	string	message to print

Example:

Code Block

language	py

printText('There is no spoon.')

...

When using this method, the global number of warnings is incremented by 1.

Arguments:

Name	Type	Description
message	string	warning message to print

Example:

Code Block

language	py

printWarning('The cake is a lie.')

...

Minimum value is 1. The tool uses the number of logic cores of the computer as a maximum.

Arguments:

Name	Type	Description
core_count	integer	core count number

Example:

Code Block

language	py

setCoreCount(2)

...

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Name

Type

Description

change_project_dir

boolean

Change project directory when loading a project file when True (default).

Keep the current project directory when False

Example:

Code Block

language	py

p = createProject()
setDirAutoChange(False)
p.load('my_path/routed-auto.nym')

...

This function allows to create a user-defined directory to stock the reports created during the execution of the flow.

Arguments:

Name	Type	Description
log_directory	string	Name of the directory to be created.

Example:

Code Block

language	py

setLogDirectory(‘TestLogDirectory’)

...

Hereafter an example with existing paths and constraints:

Existing Path \ Path in constraint	start_path\|mycell_*	start_path\|mycell_+
start_path\|mycell_12	Match	Match
start_path\|mycell_12\|some_sub_cell	Match	No match

Note:

If the user needs to use regular expressions ignoring auto-escaping of special characters, it is possible to set the constraint using back quotes as follow:

...

The method addBank allows user to configure a specific bank of the FPGA. The pads inside the defined bank will be used first to configure inputs/outputs of the HDL module. For the given bank, the configuration has two basic arguments name and dict.

Arguments:

Name	Type	Description
name	string	the name of the bank. The bank name must respect syntax of the various banks included in current FPGA variant.
dict	dictionary	the dictionary of parameters of the bank. All keys and values of the dictionary are string.

dict is a dictionary which can take the following keys:

Type	Description
voltage	voltage of the bank (V)

The voltage must be one of the following values:

...

The method addBanks allows user to configure several banks of the FPGA to be used for configuration of inputs/outputs of the HDL module. addBanks use a dictionary as an argument.

Arguments:

Name	Type	Description
dict	dictionary	the dictionary of banks. See addBank method for the list of available keys

Example:

Code Block

language	py

ioBanks = { 'IOB0'  : {'voltage': '2.5'}
                  , 'IOB1'  : {'voltage': '2.5'}
                  , 'IOB2'  : {'voltage': '2.5'}
                  , 'IOB3'  : {'voltage': '2.5'}
                  , 'IOB4'  : {'voltage': '2.5'}
                  , 'IOB5'  : {'voltage': '2.5'}
                  , 'IOB6'  : {'voltage': '2.5'}
                  , 'IOB7'  : {'voltage': '2.5'}
                  , 'IOB8'  : {'voltage': '2.5'}
                  , 'IOB9'  : {'voltage': '2.5'}
                  , 'IOB10' : {'voltage': '2.5'}
                  , 'IOB11' : {'voltage': '2.5'}
                  , 'IOB12' : {'voltage': '2.5'}
          }
project.addBanks(ioBanks)

...

The method addBlackBox allows users to define customized mapping of certain HDL modules on the specific FPGA blocks and to dispose the interface of the blocks.

Arguments:

Name	Type	Description
name	string	the name of HDL module that is intended to be custom-mapped.
type	string	the nxpython object type (further details below).
mapping	string	the mapping target (further details below).
interface	string	the interface mapping between HDL module and nxpython (further details below).

The type argument can only be overridden for specific object types. The available types are:

Type	Description
ROM	Represents a ROM
RAM	Represents a RAM

For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

Type	Mapping targets	Description
ROM	RF, RAM	A ROM can be mapped onto RF blocks or RAM blocks
RAM	RF, RAM, RAM_ECC	A RAM can be mapped onto register files (if not split read/write port) or RAM blocks or RAM blocks with error detection/correction code

The argument interface argument specifies the interface mapping between the HDL module and nxpython.

...

When setting ROM value for type argument, the nxpython interface is:

Interface	Description
AD	Address to read data from
DO	Output data
CK	Clock

Note
Used only when creating synchronous memory (with one clock)

When setting RAM value for type argument, the nxpython interface depends on the mode RAM is being used in:

RAM mode: Simple port

Interface	Description
CK	Clock
AD	Address
DI	Input data
DO	Output data
WE	Write enable
RE	Read enable (optional)

RAM mode: Split read/write port (1 port for read and 1 port for write)

Interface	Description
CK0	Read clock
AD0	Read address
DO0	Read output data
RE0	Read enable (optional)
CK1	Write clock
AD1	Write address
DI1	Write input data
WE1	Write enable

RAM mode: True dual port (2 ports for read/write)

First port:

Interface	Description
CK0	Clock
AD0	Address
DI0	Input data
DO0	Output data
WE0	Write enable
RE0	Read enable (optional)

Second port:

Interface	Description
CK1	Clock
AD1	Address
DI1	Input data
DO1	Output data
WE1	Write enable
RE1	Read enable (optional)

Example:

If the HDL design contains a micro code ROM define in VHDL as:

...

This method is used to specify the false path for the timing paths. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	the command which specifies how to get a list of timing path starting points. A valid timing starting point is an input port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)
to_list	string	the command which specifies how to get a list of timing path ending points. A valid timing ending point is an output port or a register. A valid command can be: getPort(port_name), getPorts(name_expression), getRegister(register_name), getRegisters(name_expression), getRegistersByClock(clock_name)

Example:

Code Block

breakoutMode	wide

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),getRegister('UUT2|dout_reg[61]'))

...

This method is used to add a HDL source file to the project. The file can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Name

Type

Description

library

string

name of the HDL library that contains the source file.

file

string

HDL source file, the path can be absolute or relative to the directory of the project.

file argument supports several flags for language compilation : VHDL_93, VERILOG_95, VERILOG_2K (default flag for verilog)

Example:

Code Block

language	py

project.addFile('src/simple.vhd')
project.addFile('src/complex.vhd:VHDL_93')
project.addFile('src/simple_verilog.v:VERILOG_95')
or
project.addFile('myLib', 'src/simple.vhd')

...

This method is used to add several HDL source files to the project. The files can be added to a specific library by passing its name as the first optional library argument. The default library is work.

Arguments:

Name	Type	Description
library	string	name of the HDL library that contains the source files.
fileList	list	list of HDL source files, the path can be absolute or relative to the directory of the project.

Example:

Code Block

language	py

project.addFiles(['src/simple.vhd', 'src/test.vhd'])
or
project.addFiles('myLib', ['src/simple.vhd', 'src/test.vhd'])

...

Placement of HSSL elements can also be done during instantiation (with location generic in source code).add

Arguments:

Name	Type	Description
pattern	string	A pattern to match the HSSL controller instance name. The path must be set entirely.
location	string	the requested location for the HSSL block. Valid locations are HSSLn

Example:

Code Block
project.addHSSLLocation('i_hssl_esistream\|i_HSSL_ONLY\|i_NX_HSSL_FULL\|ctrl', 'HSSL2')

...

This method is used to add a mapping directive for Synthesis flow step which overrides the default nxpython mapping behavior for a specific HDL module or instance.

Arguments:

Name	Type	Description
name	string	the name of HDL module or instance that is intended to be custom-mapped.
type	string	the target type of the directive (further details below).
mapping	string	the target mapping of the directive (further details below).

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The type argument can only be overridden for specific object types. For each type, there are some specific instances in the FPGA onto which it can be mapped. This can be specified using mapping argument. The following table presents all the available mapping targets for each type:

Type	Mapping targets
ADD	LUT, CY, DSP
LTN	LUT, CY, DSP
MUL	CY,DSP
RAM	RF, RAM, RAM_ECC, DFF
ROM	LUT, RF, RAM

Instance name must match the following pattern: ‘PATHNAME|INSTANCENAME’

...

This method is used to specify the maximum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	the command which specifies how to get a list of timing path starting points. A valid timing starting point is a register.
to_list	string	the command which specifies how to get a list of timing path ending points. A valid timing ending point is a register.
delay	integer	the required maximum delay value in ps for specified paths.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMaxDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
                        getRegister('UUT2|dout_reg[61]'), 3900)

...

This method is used to specify a file that will be used to initialize a specific memory instance.
Arguments:

Name	Type	Description
name	string	the name of the instance that is intended to be initialized from a file.
type	string	the file format (further details below).
file	integer	the name of the file to load (further details below).

The name argument can be a regular expression matching a HDL module or instance name. In order to specify whether to search for module or instance, the user has to use the getModels(...) or getInstances(...) keyword.

The available file formats are:

Type	Format
NX	NanoXplore Proprietary format

The name parameter must match the following pattern: TOPCELLNAME_INSTANCENAME

...

This method is used to specify the minimum delay path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	the command which specifies how to get a list of timing path starting points. A valid timing starting point is a register.
to_list	string	the command which specifies how to get a list of timing path ending points. A valid timing ending point is a register.
delay	integer	the required minimum delay value in ps for specified paths.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addMinDelayPath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[23]'),
                                     getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[22]'), 1200)

...

This method is used to add a HDL module definition to the current project that contains all HDL logic elements including within the model given in argument.

Arguments:

Name	Type	Description
model	string	the regular expression pattern to match the model name of the module. All regular expressions are allowed and special characters must be escaped.
instance	string	the regular expression pattern to match the instance name of the module. If instance pattern is empty, it will match any occurrence of the associated model. All regular expressions are allowed and special characters must be escaped.
format	string	the format of the internal name of the matched modules (character % is replaced by an incremental value).

Example:

Code Block

language	py

project = createProject()
project.addModule('mCntrl',      'cntrl',    'cntrl-%')

...

This method is used to specify the multicycle path for the timing paths. It is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
from_list	string	the command which specifies how to get a list of timing path starting points. A valid timing starting point is a register.
to_list	string	the command which specifies how to get a list of timing path ending points. A valid timing ending point is a register.
cycle_count	unsigned	An unsigned value that represents a number of cycles the data path must have for setup check.

Example:

Code Block
project = createProject() project.load('routed.nym') project.addMulticyclePath(getRegister('UUT1\|Gen_seq[3].seq_i\|temp_reg[1]'), getRegister('UUT2\|dout_reg[61]'), 2)

...

This method is used to create an obstruction object which will be removed from impulse resources for Place & Route steps.

Arguments:

Name	Type	Description
name	string	defines the name of the obstruction
column	unsigned	the obstruction first abscissa. A valid abscissa value must respect the tile or CGB column coordinate which is available for the selected target variant in the current project.
row	unsigned	the obstruction first ordinate. A valid ordinate value must respect the tile or CGB row coordinate which is available for the selected target variant in the current project.
width	unsigned	the number of columns from column variable.
height	unsigned	the number of rows from row variable.

Example:

Code Block
project = createProject() project.load('synthesize.nym') project.addObstruction('obstr', 10, 2, 15, 5)

...

This method allows user to configure an input/output of the HDL module into specific pad of the FPGA. For the given pad, the configuration has two basic argument (name and parameters).

Arguments:

Name	Type	Description
name	string	the HDL input/output name.
parameters	dictionary	the keys are the parameters names and the values are the parameters values.

The parameters argument is a dictionary which can take the following keys:

location (string)	inputDelayOn (boolean)	turbo (boolean)
standard (string)	inputDelayLine (integer)	signalSlope
drive (string)	outputDelayOn (boolean)	outputCapacity
weakTermination (string)	outputDelayLine (integer)	registered
slewRate (string)	differential (boolean)
termination (string)	terminationReference (string)

Note
In case of parameters are set by NX_IOB or NX_IOB_I or NX_IOB_O and by the addPad method, addPad method get the priority except for ‘location’ and ‘termination’ if ‘locked’ is enabled in the IOB primitive.

...

The I/O differential (Default False) activation is conditioned depending on standard:

standard	differential
LVDS	True (mandatory)
LVDS_STR	True (mandatory)
LVCMOS	False
SSTL	True
HSTL	True

In case of differential mode, the user must only declare the “_P” pad. The associated differential “_N” pad will be automatically set by the software with the same parameters.

...

As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and noise limitation plus power consumption:

drive	LVCMOS	LVDS	SSTL 2.5V	SSTL 1.8V	HSTL
2mA	Fmax = 50MHz	-	-	-	-
4mA	Fmax = 100MHz	-	-	-	-
8mA	Fmax = 200MHz	-	-	-	-
16mA	Fmax = 300MHz	-	-	-	-
I	-	-	8mA, Fmax=300MHz	8.6mA, Fmax=400MHz	8mA, Fmax=400MHz
II	-	-	16mA, Fmax=300MHz	13.4mA, Fmax=400MHz	16mA, Fmax=400MHz
undefined	-	3.5mA, Fmax=400MHz	-	-	-

The weakTermination key must respect the following values:

...

Min and max values depend on the variant and the bank voltage.

Voltage (V)	NG-MEDIUM		NG-LARGE		NG-ULTRA
Voltage (V)	Rmin (Ω)	Rmax (Ω)	Rmin (Ω)	Rmax (Ω)	Rmin (Ω)	Rmax (Ω)
1.2	X	X	X	X	30	84
1.5	X	X	X	X	31	88
1.8	31	85	30	85	32	92
2.5	35	100	34	102	X	X
3.3	X	X	X	X	X	X

Note
Can only be set if terminationReference is set.

...

The terminationReference key is used only if termination is set (Default '-'). It must respect the following criteria to be set to ‘Floating’ value otherwise it should always be defined as ‘VT’.

Must be set to ‘Floating’ if:

differential is set to ‘True’
weakTermination is set to ‘None’

‘VT’ otherwise

Note
Check chip datasheet to see differential feature availability on different IO banks.

...

When set to ‘True”, the turbo key (Default False) specifies that the input buffer of the pad is in turbo mode. As an example for NG-Large variant, the following array gives a trade-off between the maximum frequency reachable and power consumption:

Standard	Turbo enabled (True)	Turbo disabled (False)
LVCMOS 3.3V	Fmax = 200MHz	Fmax = 100MHz
LVCMOS 2.5V	Fmax = 300MHz	Fmax = 200MHz
LVCMOS 1.8V	Fmax = 300MHz	Fmax = 150MHz
LVCMOS 1.5V	Fmax = 300MHz	Fmax = 150MHz
LVDS	Fmax = 400MHz	Fmax = 100MHz
SSTL 2.5V	Fmax = 300MHz	Fmax = 150MHz
SSTL 1.8V	Fmax = 400MHz	Fmax = 150MHz

The registered key (Default '') allows user to merge registers into Input/Output pads. This key can take the following values:

registered	Polarity of pad
I	Input
IC	Input with tri-state management
O	Output
OC	Onput with tri-state management
IO	Input and Output
IOC	Input and Output with tri-state management

Note

Merging a register into the pad (DFR using instead of DFF) can be rejected for one of the following reasons:

Context issue: DFR cannot be initialized
Type issue: DFR can get a RESET but not a SET (Medium/Large only)
Fanout issue: Pad signal cannot be used directly (BFR) and through a pad register (DFR)
Tristate issue: Inconsistency between control and data signals

...

This method is used to configure inputs/outputs of the HDL module into specific pads of the FPGA. The argument is a dictionary that associates the HDL input/output name to a dictionary, which can contain some keys (location, type, weakTermination, slewRate, termination, inputDelayLine, outputDelayLine, differential, terminationReference, turbo) as defined in addPad(name, parameters).

Arguments:

Name	Type	Description
pads	dictionary	the keys are the HDL input/output names and the values are dictionaries of parameters.

Example:

Code Block

language	py

#LVCMOS implementation
pads = {'clk', {'location': 'IO_B1D02P', 'standard': 'LVCMOS', 'drive' :'2mA'},
	  'in_row', {'location': 'IO_B1D04P', 'standard': 'LVCMOS', 'drive' :'2mA', 'weakTermination':
            'PullUp', 'slewRate': 'Slow', 'termination': '50', 'inputDelayLine': 1, 'outputDelayLine': 2, 
           'differential': False, 'turbo': True}
          }
project.addPads(pads)

...

This method allow user to configure an input/output of the HDL module into specific pin of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments

Name	Type	Description
name	string	the HDL input/output name.
location	string	the location of the input/output.

Example:

Code Block
project.addPin('A', 'TUI200')

...

This method allow user to configure inputs/outputs of the HDL module into specific pins of the embedded FPGA. This method is reserved to embedded variants of FPGA.

Arguments:

Name	Type	Description
pins	dictionary	the keys are the HDL input/output names and the values are the locations.

Example:

Code Block

language	py

pins = {
	  'A': 'TUI200',
	 'B': 'TUI201'
          }
project.addPins(pins)

...

This method allows user to specify the value of the top design generic parameters.

Arguments:

Name	Type	Description
name	string	the name of the generic parameter.
value	string	the value of the generic parameter.

Example:

Code Block

project.addParameter('BusWidth', '16')
project.addParameter('Key_size', '2')
NB_PIPE_ROW_WG1 = 5 
NB_PIPE_ROW_WG2 = 7 
NB_PIPE_ROW_WG3 = 3 
#parameter list for VHDL design
project.addParameter('NB_PIPE_ROW_WG1', str(NB_PIPE_ROW_WG1))
project.addParameter('NB_PIPE_ROW_WG2', str(NB_PIPE_ROW_WG2))
project.addParameter('NB_PIPE_ROW_WG3', str(NB_PIPE_ROW_WG3))

...

In case of a large number of parameters, a parameter dictionary can be created consisting of the name of the parameter as a key and its respective value. Both name and value must be string.

Arguments:

Name	Type	Description
parameters	dictionary	parameters dictionary where keys are the parameters names and values the parameters values.

Example:

Code Block
parameters = {'BusWidth': '16', 'Key_size': '2', ...} project.addParameters(parameters)

...

Placement of PLL elements can also be done during instantiation (with location generic in source code).

Arguments:

Name	Type	Description
pattern	string	A pattern to match the PLL instance name. The path must be set entirely.
location	string	the requested location for the PLL. Valid locations are CKGn.PLL1

Example:

Code Block

#placing pll0, pll1, pll2, pll3 in different CKGs
project.addPLLLocation('pll0', 'CKG1.PLL1')
project.addPLLLocation('pll1', 'CKG2.PLL1')
project.addPLLLocation('pll2', 'CKG3.PLL1')
project.addPLLLocation('pll3', 'CKG4.PLL1')
#placing a PLL located in a sub-hierarchy of the design
project.addPLLLocation('FIR_MF|CLKG|PLL_20_160', 'CKG4.PLL1')

...

This method is used to create a region among the FPGA resources where HDL elements will be placed during Place step.

Arguments:

Name	Type	Description
name	string	defines the name of the region
column	unsigned	the region first abscissa. A valid abscissa value must respect the tile or CGB column coordinate which is available for the selected target variant in the current project.
row	unsigned	the region first ordinate. A valid ordinate value must respect the tile or CGB row coordinate which is available for the selected target variant in the current project.
width	unsigned	the number of columns from column variable.
height	unsigned	the number of rows from row variable.
exclusive	boolean	set if the region is exclusive

Example:

Code Block

language	py

project = createProject()
p.addRegion('ALU',      13, 6, 14, 6)
p.addRegion('REGISTER', 22, 6, 23, 6, True)

...

This method is used to place an instance in the I/O ring of the FPGA. addRingLocation can be used instead of addPLLLocation, addWFGLocation or addPin.

Example:

Name	Type	Description
name	string	the name of the instance. The path must be set entirely.
location	string	the spot in which to set the instance.

Example:

Code Block

language	py

project.addRingLocation('PLL0','CKG1.PLL1')
project.addRingLocation('WFG_3','CKG4.WFG_C1')

...

In case of a large number of instances to be placed in the I/O Ring, a dictionary can be created consisting in the name of the instance as a key and its association location. Both name and location must be string.

Arguments:

Name	Type	Description
dictionary	dictionary	dictionary where keys are the names and locations of the instances to be placed in the ring.

Example:

Code Block
rings = { 'PLL0' : 'CKG1.PLL1', 'PLL1' : 'CKG2.PLL1', 'WFG_0' : 'CKG1.WFG_C1', 'WFG_1' : 'CKG2.WFG_C1' } project.addRingLocations(rings)

...

This method is used to add an extra directory containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Name	Type	Description
directory	string	name of the directory containing Verilog files. Can be in absolute or relative.

Example:

Code Block

language	py

project.addVerilogIncludeDirectory('include’)
or
project.addVerilogIncludeDirectory('../lib’)

...

This method is used to add several extra directories containing Verilog files to the project. This is used when the included files are external to the working directory.

Arguments:

Name	Type	Description
directoryList	list	list of the directories containing Verilog files. Can be in absolute or relative.

Example:

Code Block
project.addVerilogIncludeDirectories(['include’, ‘../lib’])

...

This method is used to add a parameter definition for Verilog files.

Arguments:

Name	Type	Description
name	string	name of the parameter.
value	string	value of the parameter.

Example:

Code Block

language	py

project.addVlogDefine('G_DATA_SIZE’,'8')

...

This method is used to add parameters definition for Verilog files.

Arguments:

Name	Type	Description
dictionnary	dictionnary	dictionnary of parameters.

Example:

Code Block

language	py

project.addVlogDefines({'G_DATA_SIZE’:'8','G_ADDR_SIZE’:'16'})

...

Placement of WFG elements can also be done during instantiation (with location generic in source code).

Arguments:

Name	Type	Description
name	string	the name of the instance. The path must be set entirely.
location	string	the requested location.

Valid locations depend on the variant:

NG-MEDIUM	CKG[1−4].WFG_R[1−2]
	CKG[1−4].WFG_M[1−3]
	CKG[1−4].WFG_C[1−3]
NG-LARGE	CKG[1−4].WFG_R[1−3]
	CKG[1−4].WFG_M[1−3]
	CKG[1−4].WFG_C[1−4]

Example:

Code Block

language	py

project.addWFGLocation('wfg_0', 'CKG2.WFG_M3)

...

This method is used to apply a Synopsys Design Constraints (SDF) file to a project for STA or TimingDriven purpose.

Arguments:

Name	Type	Description
filePath	string	path of the SDF file.

Example:

Code Block

language	py

project.applySdcFile(./sdc_directory/constraints.sdc)

...

If no argument is set, constraints for the whole fabric are cleared.

Arguments:

Name	Type	Description
regionName	string	Region Name. Optional argument.

Example:

Code Block
project = createProject() project.setSite('i_cpt_0\|s_cpt_out_reg[0]', 'TILE[3x2]') project.clearFabricPreplacedConstraints() project.setSite('i_cpt_0\|s_cpt_out_reg[0]', 'TILE[4x2]')

...

This method allows to confine a module into a user defined region of the FPGA.

Arguments:

Name	Type	Description
name	string	the module name.
region	string	the region to confine the module in.

When a module is added to the current project with command, nxpython will generate a module name with automatic incremental syntax in case of listing different modules with similar names.

...

constrainModule(hierarchy, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

Arguments:

Name	Type	Description
hierarchy	string	the line corresponding to the module found in hierarchy.rpt log file. The path must be set entirely.
moduleName	string	the name to identify the module in GUI and log files.
type	string	impact the strength of constraint related to neighbor modules. ‘Hard’ specifies all logic to be constrained in the region. ‘Soft’ implies some logic could be placed outside of the region to be connected with external logic.
leftCol	integer	the number of the most left column of the region.
topRow	integer	the number of the most top row of the region.
width	integer	the width of the region (in number of columns).
height	integer	the height of the region (in number of rows).
regionName	string	the name to identify the region (in number of rows).
exclusive	boolean	exclusive : can be ‘True’ or ‘False’

Example:

Code Block

breakoutMode	wide

#hierarchy argument is extracted from hierarchy.rpt     
# hierarchy, module name, type, col, row, width, height, regionname, exclusive
project.constrainModule('|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12,  19,   3,     'TIMER',    False)

...

constrainPath(sourceList, targetList, moduleName, type, leftCol, topRow, width, height, regionName, exclusive)

Arguments:

Name	Type	Description
sourceList	stringList	the list of source register names or patterns. All regular expressions are allowed and special characters must be escaped.
targetList	stringList	the list of target register names or patterns. All regular expressions are allowed and special characters must be escaped.
moduleName	string	the name to identify the module in GUI and log files.
type	string	impact the strength of constraint related to connected resources. ‘Hard’ specifies only the logic contained in the path is constrained. ‘Soft’ implies some additional resources connected to the logic contained in the path could be placed in the region too.
leftCol	integer	the number of the most left column of the region.
topRow	integer	the number of the most top row of the region.
width	integer	the width of the region (in number of columns).
height	integer	the height of the region (in number of rows).
regionName	string	the name to identify the region (in number of rows).
exclusive	boolean	exclusive : can be ‘True’ or ‘False’

Example:

Code Block

breakoutMode	wide
language	restructuredtext

 #sourceList, targetList, module name, type, col, row, width, height, region name, exclusive
project.constrainPath(['cntrl|state_reg*'], ['cntrl|state_reg*', 'cntrl|*Write_reg'], 'TEST', 6, 2, 1, 1, 'TEST', True)

...

This method is used to create a clock constraint of a timing point. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
target	string	the command which specifies how to get a clock related point. A valid command can be: getPort(port_name), getRegisterClock(register_name) (or getRegister(register_name)) and getClockNet(clock_net_name).
name	string	user clock name of the created clock.
period	unsigned	the period value in ps.
rising	unsigned	specific rising edge in ps for clock waveform. Range: [0, period[ (default value is 0).
falling	unsigned	specific falling edge in ps for clock waveform. Range: ]rising, rising + period] (default value is period/2).

Note
The name of the clock net is case sensitive

...

This method is used to create an internally generated clock constraint at a timing point. This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
source	string	the command which specifies how to get a source clock related point. A valid command can be: getClock(), getPort(port_name), getRegisterClock(register_name) (or getRegister(register_name)), getClockNet(clock_net_name), getWFGOutput(wfg_name)
target	string	the command which specifies how to get a clock related point. A valid command can be: getRegisterClock(register_name) (or getRegister(register_name)), getClockNet(clock_net_name)
Name	string	user clock name of the generated clock
relationship	dictionary	the relationships for computing clock wave of generated clock from master clock. All valid parameters can be: MultiplyBy : unsigned DivideBy : unsigned DutyCycle : unsigned (1 to 99) Phase : unsigned (0 to 359) Offset : integer (delay in ps) Edges : list [unsigned, unsigned, unsigned] (in non- decreasing order) EdgeShift : list [integer, integer, integer] (delay in ps)

Note
Frequency-based and edge-based relationships are mutually exclusive

...

The export is different from the save() method as it is done during the second step of synthesis.

Arguments:

Name	Type	Description
file	string	path of the output file can be absolute or relative to the directory of the project.
options	dictionary	dictionary that contains optional configuration

The options dictionary must contain at least the coreName key. The following keys are available:

Name	Description
coreName	the name of the top entity in the IPCore (default is top cell name during synthesis)
obfuscate	if set to ‘Yes’, the generated code is obfuscated (default is ‘No’)
encrypt	used to encrypt the generated file using IEEE P1735 standard. If set to ‘None’, the file is not encrypted, otherwise it is and the value corresponds to the software targeted: ‘NX’: to reuse file in impulse ‘MGC’: to reuse file in QuestaSim ‘All’: to reuse the file in impulse and / or QuestaSim
author	author information used in the encrypted file header
license	license information used in the encrypted file header

Example:

Code Block

project = createProject()
project.load('/home/user/example/vhdl/simple/native.nym')
options = { ‘coreName’: ‘IPCore’, ‘encrypt’: ‘All’ }
p.exportAsIPCore(‘IPCore.vhd’, options)
p.synthesize()

exportPlacement()

This method is used to export all placement constraints in order to be re-imported.

Example:

Code Block

breakoutMode	wide

project.exportPlacement()

exportRegions()

This method is used to export all constrainModule constraints in the console. It can be useful if the user modified the region location or size and want to get new constraints to copy them in the script.

...

This method is used to export all setSite constraints in a file. It can be useful in order to keep all TILE locations.

Name	Type	Description
projectVariable	string	the name of the project variable (usually ‘p' or 'project’).
fileName	string	file name to generate constraints into.

Example:

Code Block

breakoutMode	wide

project.exportSites('p','site_constraints.py')

...

This method is used to save the bitstream configuration file to disk. The extension of the target file must be .nxb

Arguments:

Name	Type	Description
file	string	path of the output file can be absolute or relative to the directory of the project.

Example:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
project.generateBitstream('bitstream.nxb')

...

This method is used to generate routed netlist and SDF file.

Arguments:

Name	Type	Description
filePath	string	path of the output file without extension

Example:

Code Block

breakoutMode	wide
language	py

project.route()
project.generateSTANetlist(./output_files/routed_sta_file)

...

This method is used to change the Device ID in the bitstream header before generating it.

Arguments:

Name

Type

Description

id

integer

id value in decimal in the range [0;15].

Value 0 is the default Device ID.

Value 15 is the broadcast mode.

Example:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/routed.nym')
p.setDeviceID(10) #Set Device ID to 0xA
project.generateBitstream('bitstream.nxb')

...

This method is used to get lowskew signals or potential candidates to be lowskew signals. It gives a table of impacted lobes for each lowskew signal

Arguments:

Name	Type	Description
ignoreTop	boolean	ignore top level instances in fanout count.
showCandidates	boolean	show candidates to be lowskew signals.

Example:

Code Block
project.getLowskewSignals(No,Yes) project.getLowskewSignals(No) project.getLowskewSignals()

...

Output:

Code Block
NG-MEDIUM

importPlacement([filename], [regions], [modules], [importAll])

This method is used to re-import exported placement constraints.

Arguments:

Name	Type	Description
filename	string	Path to the JSON file containing placement constraints. By default “placementConstraints.json”.
regions	list of strings	List of regions to be imported. All instances of all modules in the regions are imported. By default, all regions are imported.
modules	list of strings	List of all modules to be imported if not already selected by the region argument.
importAll	boolean	If True, all instances are selected. If False, only instances locked by a constraint are selected.

Example:

Code Block

breakoutMode	wide

project.importPlacement('my_placement_constraints.json',['REGION_0','REGION_1'],['MODULE_2_1', 'MODULE_3_2'],True)

initRegister(command, value)

This method is used to write in registers during the generation of bitstream.

Arguments:

Name	Type	Description
command	string	name of the command register to write in.
value	string	value to be write in the command register (in hexadecimal format).

Example:

Code Block
project = createProject() project.load('/home/user/example/vhdl/simple/routed.nym') project.initRegister('SPI_CTRL', '0x01f4003f') project.generateBitstream('bitstream.nxb')

...

This method is used to limit a lowskew signal to be used in only specified lobes.

Arguments:

Name	Type	Description
signal	string	name of the signal.
lobes	string	list of specified allowed lobes for the lowskew signals. Lobes must be separated by “,” character

Example:

Code Block
project.limitLowskew('clk_right','Rx1,Rx2,Rx3,Rx4')

...

This method is used to print all available pads for a bank or for all banks of a variant .

Arguments:

Name	Type	Description
name	string	name of the IO bank.

Example:

Code Block
project.listAvailableLocations() project.listAvailableLocations('IOB10')

...

This method is used to load a previously saved project from disk. The input format (file extension) must be .nym (impulse archive).

Arguments:

Name	Type	Description
file	string	impulse archive file (extension must be .nym).

Path of the input file can be absolute or relative to the directory of the project.

...

the aperture can only be edited before the execution of Place flow steps

Arguments:

Name	Type	Description
column	unsigned	the aperture first abscissa. A valid abscissa value must respect the tile or CGB column coordinate which is available for the selected target variant in the current project.
row	unsigned	the aperture first ordinate. A valid ordinate value must respect the tile or CGB row coordinate which is available for the selected target variant in the current project.
width	unsigned	the number of columns from column variable.
height	unsigned	the number of rows from row variable

Example:

Code Block

language	py

project = createProject()
project.load('synthesize.nym')
project.modifyAperture(10, 2, 15, 5)

...

This method is used to modify the location or the size of an existed region.

Arguments:

Name	Type	Description
name	string	name of the region.
column	integer	the number of the most left column of the region.
row	integer	the number of the most top row of the region.
width	integer	the width of the region (in number of columns).
height	integer	the height of the region (in number of rows).
exclusive	boolean	region is exclusive or not

Example:

Code Block
project.addObstruction('OBSTR_0', 10, 8, 10, 2) project.modifyObstruction('OBSTR_0', 10, 8, 10, 3)

...

Parameters that only affect the configuration and not the placing can be changed at any time.

Arguments:

Name	Type	Description
name	string	IO name.
parameters	dictionary	Configuration parameters.

Note
After synthesis, the following parameters cannot be modified : location, differential and registered.

...

This method is used to modify the location or the size of an existed region.

Arguments:

Name	Type	Description
name	string	name of the region.
column	integer	the number of the most left column of the region.
row	integer	the number of the most top row of the region.
width	integer	the width of the region (in number of columns).
height	integer	the height of the region (in number of rows).
exclusive	boolean	region is exclusive or not

Example:

Code Block
project.constrainModule('\|-> timer [ Inst_timer ]', 'TIMER_MOD', 'Hard', 13, 12, 19, 3, 'TIMER', False) project.modifyRegion('TIMER', 10, 8, 19, 3)

...

This method allows to progress through project to a given flow step.

Arguments:

Name	Type	Description
step	string	name of the global step [Synthesis, Place or Route].
number	unsigned	number in the global step [(1 to 2), (1 to 5) or (1 to 3)]. Synthesize step takes (1 to 2) for number, Place step takes (1 to 5) and Route step takes (1 to 3) for number.

Example:

Code Block

language	py

project = createProject()
project.load('/home/user/example/vhdl/simple/synthesized.nym')
project.progress('Place', 3)

...

This method avoids local lowskew signal to be converted in global lowskew signal.

Arguments:

Name	Type	Description
signal	string	name of the signal.

Example:

Code Block

language	py

project.rejctLowskew('sub_module0|local_reset')

...

This method allows to remove a file from a project.

Arguments:

Name	Type	Description
libName	string	name of the library. Default is work.
filePath	string	path to the file.

Example:

Code Block

language	py

project.addFile('work','sub_modul_0.vhd')
project.addFile('work','sub_modul_1.vhd')
project.removeFile('work','sub_modul_0.vhd')
project.removeFile(sub_modul_1.vhd')

...

This method does not

Arguments:

Name	Type	Description
libName	string	name of the library. Default is work.
fileList	list	list of files.

Example:

Code Block

language	py

project.addFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])
project.removeFiles('work', ['sub_modul_0.vhd', 'sub_modul_1.vhd'])

...

This method is used to destroy a given obstruction object.

Arguments:

Name	Type	Description
name	string	the name of the obstruction to be destroyed

Example:

Code Block

language	py

project.addObstruction('obstr', 10, 2, 15, 5)
project.removeObstruction('obstr')

...

This method is used to destroy a given region.

Arguments:

Name	Type	Description
name	string	the name of the region to be destroyed

Example:

Code Block

language	py

project.addRegion('CNTRL',     4, 6,  2, 1)
project.removeRegion('CNTRL')

...

This method reports the design complexity, clock domain by clock domain, indicating the logic depth for all paths of the design and illustrates it with a chart in HTML format:

Name	Type	Description
html_file	string	output HTML file name.

Example:

Code Block
project.reportDesignComplexity('design_complexity.html')

...

This method reports the instances utilization of the programmed design on the current variant. Three tables are printed. The first one contains values for all types of instances. The instances are grouped by categories:

4-LUT	Look up table with a maximum of 4 connected entries

DFF	DFF register
X-LUT	"X-LUT" as defined in datasheet
4-Bits Carry	"4-bits carry look ahead" as defined in datasheet
Register file block	"Register files" as defined in datasheet
Cross domain clock	A two "DFF" pipeline optimized for metastability problem
Clock switch	Elements which logically interrupt a clock without shortening current cycle
Digital signal processor	"DSP" as defined in datasheet
Memory block	"Memory" as defined in datasheet
WFG	"WFG" as defined in datasheet
PLL	"PLL" as defined in datasheet

The second table gives more details about 4-LUTs utilization:

Synthesized from HDL	Number of LUTs that have been instantiated from the design
Used by DFF	Number of LUTs that are used by DFFs
Used by CY	Number of LUTs that are occupied by Carrys
Used by RF	Number of LUTs that are occupied by RFs
Used by CKS	Number of LUTs that are occupied by CKSs
Used by Internal	Number of LUTs created while processing the design to solve architectural constrains
Used by Total	Total number of LUTs NOT instanciated from the design
4-LUT count	Overall use of 4-LUT for the current design

The last table gives detailed information about the use of registers:

SFE	Number of DFF registers used by LUTs
Carry	Number of DFF registers used by Carries
DFF sub-total	Total count of DFF registers
CKS	Number of registers used in CKSs
RF	Number of registers used in RFs
DSP	Number of registers used in DSPs
RAM	Number of registers used in RAMs
Pads	Number of DFFs merged in pads
Total	Overall use of registers for the current design

This method takes no argument.

...

This method reports the lowskew signals:

Name	Type	Description
logfile	string	path to the logfile to report (without .log extension).

Example:

Code Block
project.reportLowskewSignals('lowskew_report')

...

This method reports the ports found in HDL source and the ones manually added by user in the project. The report displays the following information:

Name	Name of the HDL port
Direction	Direction of the port (can be input, output or inout)
Location	Pad location associated to the port (can be set by the user or automatically set by impulse)
Type	Type of the associated pad
SlewRate	Slew rate value of the associated pad
InputDelayLine	Input delay line of the associated pad
OutputDelayLine	Output delay line of the associated pad
Differential	True if the associated pad is in differential mode
Turbo	True if the associated pad is in turbo mode

This method takes no argument.

...

This method is used to save the current project into a impulse archive (.nym), a design netlist (.v or .vhd) or to generate a sdf file containing delays of the design supporting bestcase, worstcase and typical scenarios.

Arguments:

Name	Type	Description
file	string	Target file (extension must be .nym, .v, .vhd or .sdf )
conditions	string	STA environment conditions. Only for SDF generation.

Project must be routed to save a .sdf file

...

This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
conditions	string	the command which specifies the conditions for static timing analysis.

Example:

Code Block

language	py

project.setAnalysisConditions(WorstCase)

...

This constraint is used by timing driver algorithms and static timing analysis.

Arguments:

Name	Type	Description
value	unsigned	the valid constant values are 0 or 1
net_list	string	the command which specifies how to get one or several nets. A valid command can be: getNet(net_name), getNets(net_name_expression), getPort(port_name), getPorts(port_name_expression)

Setting a case value on a net results in disabling timing analysis through the emitter pin and all the receiver pins of the net. It means that timing paths through those pins are not considered.

The constant value is propagated thro

...

A clock cannot be in a different group from itself.

Arguments:

Name	Type	Description
group1_list	string	the command which specifies how to get a group of clocks. A valid clock should be a clock created by command "createClock". A valid command can be: getClock(clock_name) and getClocks(name_expression).
group2_list	string	same as the argument "group1_list"
option	string	a valid option can be 'asynchronous' or 'exclusive': Asynchronous clocks are those that are completely unrelated. Exclusive clocks are not actively used in the design at the same time

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet(CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet(CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'),getClock('clk2'), 'exclusive')

...

This method is used to set a description to a project.

Arguments:

Name	Type	Description
description	string	description of the project.

Example:

Code Block

language	py

project = createProject()
project.setDescription('Impulse project for training')

...

This method is used to change project directory.

Arguments:

Name	Type	Description
directory	string	new directory path of the project.

Example:

Code Block

language	py

project = createProject()
project.setDirectory('./new_dir')

...

The focus can only be edited before the execution of Place flow steps.

Arguments:

Name	Type	Description
column	unsigned	the focus abscissa. A valid ordinate value must respect the tile or CGB column coordinate which is available for the selected target variant in the current project.
row	unsigned	the focus ordinate. A valid ordinate value must respect the tile or CGB row coordinate which is available for the selected target variant in the current project.

Example:

Code Block

language	py

project = createProject()
project.load('synthesize.nym')
project.setFocus(4, 4)

...

This method is used to limit the number of GCK at the end of Placing step 2.

Arguments:

Name	Type	Description
count	integer	maximum value of GCK.

Note
This method must be used only for NG-ULTRA family.

...

This method specifies the data arrival times at the specified input ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
clock	string	the command which specifies how to get a clock specified. A valid clock should be a clock created by command "createClock". A valid command: getClock(clock_name).
clock_node	string	specifies that input delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall".
minimum_delay	integer	applies value as minimum data arrival time.
maximum_delay	integer	applies value as maximum data arrival time.
port_list	string	the command which specifies how to get a list of input pads. A valid command can be: getPort(port_name), getPorts(name_expression).

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500,getPort('RST'))

...

This method is used to set the value of a nxpython option. An option can be set at any time of the design flow.

Arguments:

Name	Type	Description
name	string	the name of the option
value	string	the value of the option

The available options are:

Name

Default

Description

'AllowCascadedGCK'

‘No’

‘No’: Prohibit GCK cascade

‘Yes’: Allow GCK cascade

'Autosave'

'Yes'

Enable automatic protect save after each flow step.

'BypassingEffort'

'Medium'

Specify the DFF load and reset spreading level into the low-skew network (can be 'Low', 'Medium' or 'High'):

Low: all Load and Resetare sent in low skew

Medium: Impulse choose an effective balance

High: all Load and Reset are routed in common parts ( high routing constraint)

'CMICLatency'

'0'

Additional delay between 2 CMIC scans.

Expressed in number of BSM clock cycles.

'CongestionEffort'

'High'

Specify the routing resources limit per tile to leave and enter in the tile (can be 'Low', 'Medium' or 'High'):

Low : less routing constraints but may need further more tiles and CGBs
Medium : balanced routing constraints but may need more tiles and CGBs
High : all routing resources

'Dynamic'

'No'

Refresh view while algorithms are running.

'DefaultFSMEncoding'

'OneHot'

Default encoding of finite state machine (can be 'OneHot', 'OneHotSafe', 'OneHotSafeExtra' or 'Binary'):

Binary: minimum amount of bit is used
OneHot: only one bit changes per state. Others case is not handled.
OneHotSafe: detects invalid state where all bits are ‘0’ and returns to others case.
OneHotSafeExtra: detects any invalid state where all bits are '0' or more than one bit to ‘1’ and returns to others case. Additional logic is implemented.

Example for binary encoding with 3 states:

Code Block
“00”, “01”, “10”

Example for one hot encoding with 3 states:

Code Block
“001”, “010”, “100”

Note

If state encoding is forced by the RTL code with the following example, the FSM is not reported in logs:

attribute enum_encoding of t_state_type : type is "01 10"

'DefaultRAMMapping'

'AUTO'

Default mapping of RAM (can be 'AUTO', 'RF', 'RAM' or 'RAM_ECC').

'DefaultROMMapping'

'AUTO'

Default mapping of ROM (can be 'AUTO', 'LUT', 'RF', 'RAM' or 'RAM_ECC').

'DensityEffort'

'Low'

Specify the tile instance resources allowed per tile like DFF,LUT, … (can be 'Low', 'Medium' or 'High'):

Low: less resources (less routing constraints but may need more tiles and CGBs): 70% is allowed
Medium: well suited resources: 80% is allowed
High: more resources (more routing constraints): 90% is allowed

'DisableAdderBasicMerge'

'No'

Disable carry optimization around adders and subtractors.

'DisableAdderTreeOptimization'

'No'

Disable adder mux reordering and adder tree balancing.

'DisableAdderTrivialRemoval'

'No'

Disable simplification of adder that could fit in 1 or 2 LUTs.

'DisableAssertionChecking'

'No'

Deactivate VHDL assertions.

'DisableDSPAluOperator'

'No'

Disable merge of ALU within inferred DSP.

'DisableDSPFullRecognition'

'No'

Disable inference of DSP.

'DisableDSPPreOperator'

'No'

Disable merge of pre-operator within inferred DSP.

'DisableDSPRegisters'

'No'

Disable merge of registers within inferred DSP.

'DisableRegisterMergeInDspForAdd'

‘No’

Disable merge of registers in DSP when used as adder

'DisableKeepPortOrdering'

'No'

Disable keep port ordering used in source files when generating HDL netlists.

'DisableLoadAndResetBypass'

'No'

Disable load and reset signal bypass on DFF.

'DisableRAMAlternateForm'

'No'

Disable recognition of registered address read port.

'DisableROMFullLutRecognition'

'No'

Disable merge of ROM recognized as LUT with logic.

'DisableRAMRegisters'

'No'

Disable merge of registers within inferred RAM.

‘ExhaustiveBitstream’

‘No’

Can be used to force generation of all configurations and contexts in bitstream (can be ‘No’, ‘Config’, ‘Context’ or ‘ConfigContext’).

'GenerateBitstreamCMIC'

'No'

Generate bitstream with CMIC.

‘InitializeContext’

'No'

Initialize all DFF, RFB and RAM of the chip.

It increases the bitstream size.

'IgnoreRAMFlashClear'

'No'

Do not output error when recognizing a RAM with flash clear.

'ManageAsynchronousReadPort'

'No'

If 'Yes', detect asynchronous read port in memories and repair it in synchronous read port. The read port receive the reversed write clock. It can slow down the design and sometimes may cause invalid behavior.

'ManageUnconnectedOutputs'

'Error'

Undriven outputs of HDL modules are treated as ‘Error', 'Ground', 'Power' or 'Preserve’.

Error: Generates an error

Ground: Connect to '0'

Power: Connect to '1'

Preserve: Preserve attribute set to avoid optimization

'ManageUnconnectedSignals'

'Error'

Undriven internal signals of HDL modules are treated as ‘Error', 'Ground', 'Power' or 'Preserve’.

Error: Generates an error

Ground: Connect to '0'

Power: Connect to '1'

Preserve: Preserve attribute set to avoid optimization

'ManageUninitializedLoops'

'No'

Remove reset-less looped DFF causing extra-mapping and 'X' values in simulation (can be 'No', 'Power, ''Ground').

'MappingEffort'

'Low'

Effort for an optimized mapping in terms of primitive instance merging and simplification (can be 'Low', 'Medium' or 'High'):

Low: almost no optimization
Medium: balanced optimizations
High: almost all optimizations

'MaxRegisterCount'

'2500'

Maximum number of registers handled per HDL module (not the whole design) by the synthesizer.

‘OptimizedMux’

‘Yes’

If set to 'Yes', impulse will identify and convert every mux in the corresponding optimized 4-LUT structure.

'PartitioningEffort'

'Medium'

Define the size of the netlist subset which will be further optimized for timing goals achievement (can be 'Low', 'Medium' or 'High') :

Low: small part
Medium: medium part
· High: huge part

Info
Option is activated only if TimingDriven option is enabled.

'PolishingEffort'

'Medium'

It allows to regenerate locally a signal in TILE which in normal way should be provide by an others TILE in order to reduce utilization of routing resources.

Low: deactivate
Medium: can replicate LUT
High: can replicate LUT and DFF

'ReadyOffWithSoftReset'

‘Yes’

Only available for NG-ULTRA variant.

It links the ready falling edge to soft reset enabling during the power off reset sequence.

‘ReplicationApproval’

‘Yes’

Allow replication in a close TILE if not possible in the current TILE.

No: Do not allow replication
Yes: Allow replication

'RoutingEffort'

'Medium'

Routing Optimization level in terms of routing instances (can be 'Low', 'Medium' or 'High'):

Low: no optimization
Medium: balanced optimizations
High: further optimizations but time consuming

‘SaveTiming'

‘No’

Save STA in .nym project files

No: STA is not saved in project files
Yes: STA is saved in project files

‘Seed’

‘1789’

Seed for placing algorithm start. Depending on the seed, instances are created in a different order and placed so.

Can be used in order to generate several Place & Route with the same synthesized project.

'SetRunAfterContext'

‘No’

Indicate the sequence in the bitstream between run (routing instances enable) and context (initialization values for DFF, RFB, RAM).

No: Run is set before Context
Yes: Run is set after Context

'SharingEffort'

'Medium'

Enables the insertion in lowskew network signal with fanout above the SharingFanout threshold.

Low: Lowskew insertion disabled
Medium/High: Lowskew insertion enabled

Medium and High have the same impact.

'SharingFanout'

'100'

Fanout threshold to insert signal in lowskew network.

This option has an impact only if SharingEffort is set to Medium or High.

‘SimplifyRegions’

‘Yes’

Clear module and region database:

delete modules without instance
delete regions without module
merge identical regions

‘SytemOutputDriven’

'No'

Increase placing close to the ring for instances communicating with.

No: No priority for these instances in algorithm
Yes: Allow priority for these instances in alogrithm

'TimingEffort'

‘High’

Indicates level of iterations for TimingDriven algorithm.

Low: no iteration
Medium: a few iteration
High: more iterations

Info
Option is activated only if TimingDriven option is enabled.

Note
For heavy designs, runtime can increase drastically depending on number of iterations.

'UnusedPads'

'Floating'

State in which the pads must be set when not used. Values can be 'Floating','WeakPullUp', 'WeakPullDown'. Note that when the state is different from 'floating', all the pads are serialized in the bitstream.

Note that ‘WeakPulldown’ value is not available on NX1H35S component.

‘VariantAwareSynthesis’

‘Yes’

If set to ‘Yes’ synthesis will automatically map to equivalent resource when specific resource is depleted. For example using DSP when there are no more CY available (can be ‘Yes’ or ‘No’).

Note
Bigger the ‘MaxRegisterCount’ value, bigger the memory consumption used by the synthesizer.

Some options can affect only specific processes of the design flow. Following, a table of the specific processes per options:

Name	Synthesize	Place	Route	Bitstream
'Autosave'	X	X	X	X
'BypassingEffort'		X
'CongestionEffort'		X
'CMICLatency'				X
'Dynamic'		X	X
'DefaultAssertionChecking'
'DefaultFSMEncoding'	X
'DefaultRAMMapping'	X
'DefaultROMMapping'	X
'DensityEffort'		X
'DisableAdderBasicMerge'	X
'DisableAdderTreeOptimization'	X
'DisableAdderTrivialRemoval'	X
'DisableAssertionChecking'	X
'DisableDSPAluOperator'	X
'DisableDSPFullRecognition'	X
'DisableDSPPreOperator'	X
'DisableDSPRegisters'	X
‘DisableRegisterMergeInDspForAdd’	X
'DisableKeepPortOrdering'	X
'DisableLoadAndResetBypass'	X
'DisableRAMAlternateForm'	X
'DisableRAMRegisters'	X
'DisableROMFullLutRecognition'	X
‘ExhaustiveBitstream’				X
'GenerateBitstreamCMIC'				X
'IgnoreRAMFlashClear'	X
'InitializeContext'				X
'ManageAsynchronousReadPort'	X
'ManageUnconnectedOutputs'	X
'ManageUnconnectedSignals'	X
'ManageUninitializedLoops'	X
'MappingEffort'	X
'MaxRegisterCount'	X
‘OptimizedMux’	X
'PartitioningEffort'		X
'PolishingEffort'		X
'ReadyOffWithSoftreset'				X
‘ReplicationApproval’		X
'RoutingEffort'		X
'SetRunAfterContext'				X
‘SimplifyRegions’		X
‘SystemOutputDriven’		X
‘TimingEffort’		X
'UnusedPads'				X
‘VariantAwareSynthesis’	X

Example:

Code Block

language	py

project.setOption('MappingEffort', 'Medium')

...

This method allows user to set the values of several nxpython options. The options can be set at any time of the design flow.

Arguments:

Name	Type	Description
options	dictionary	the keys of the dictionary are the options names and the values are the options values.

For a list of all available options, see setOption(name, value)

...

This method specifies the data arrival times at the specified output ports relative to the clock. The clock must refer to a clock name in the design. This constraint is used by timing driven algorithms and static timing analysis.

Arguments:

Name	Type	Description
clock	string	the command which specifies how to get a clock specified. A valid clock should be a clock created by command "createClock". A valid command can be: getClock(clock_name).
clock_mode	string	specifies that output delay is relative to the falling or rising edge of the clock. It must be "rise"' or "fall".
minimum_delay	integer	applies value as minimum data arrival time.
maximum_delay	integer	applies value as maximum data arrival time.
port_list	string	the command which specifies how to get a list of output pads. A valid command can be: getPort(port_name), getPorts(name_expression).

Example:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setOutputDelay(getClock('CLK'), 'rise', 1000, 1500, getPorts('dataout[`[0−5]`]'))

...

If too many instances have been given with instancePattern, setSite returns false
If instances given with instancePattern have been placed successfully, setSite returns true

Arguments:

Name	Type	Description
instancePattern	string	the pattern of the instances.
siteName	string	the name of the site. Must be a TILE/CGB element.

Example:

Code Block

p.setSite('i_cpt_0|s_cpt_out_reg[0]','TILE[2x2]')#DFF
p.setSite('i_cpt_1|LessThan_L23/lut_0','TILE[5x2]')#LUT
p.setSite('i_cpt_2|add_L24_stage1','TILE[7x2]')#CY
p.setSite('i_RAM_small|s_mem*','TILE[11x2]')#RF
p.setSite('i_RAM_big|s_mem*','TILE[11x4]')#RAM
p.setSite(i_cpt_3|add_L24*','CGB[9x4]:L')#DSP

...

This method is used to set the name of the HDL top module. If the HDL module is defined inside a library, the name of the library can be passed as the first argument.

Arguments:

Name	Type	Description
library	string	name of the HDL library that contains the top module.
name	string	name of the HDL top module.

Example:

Code Block

language	py

project.setTopCellName('simple')
or
project.setTopCellName('myLib', 'simple')

...

This method is used to set the variant of the project. The default value of the variant is 'NG-MEDIUM'.

Arguments:

Name	Type	Description
variant	string	the name of the variant.

Example:

Code Block
project = createProject() project.setVariantName('NG−MEDIUM') project.setVariantName('NG−LARGE') project.setVariantName('NG−ULTRA')

...

This method is used to add a testBench file. The file can be added to a specific library by passing its name as the first optional argument 'library'. The default library is 'work'.

Arguments:

Name	Type	Description
library	string	Name of the HDL library that contains the testbench file.
testBench	string	Testbench file relative to the project directory.

Example:

Code Block

language	py

simulator.addTestBench(‘testbench.vhd’)
or
simulator.addTestBench(‘myLib’, ‘testbench.vhd’)

...

This method is used to add several testbench files. The files can be added to a specific library by passing its name as the first optional argument library. The default library is work.

Arguments:

Name	Type	Description
library	string	Name of the HDL library that contains the testbench file.
fileList	list	List of testbench files relative to the project directory.

Example:

Code Block

language	py

simulator.addTestBenchs([‘testbench1.vhd’, ‘testbench2.vhd’])
or
simulator.addTestBenchs(‘myLib’, [‘testbench1.vhd’, ‘testbench2.vhd’])

...

This method is used to add a signal which will be displayed in vsim. It is also possible to add all the available waves by passing '*' as argument.

Arguments:

Name	Type	Description
wave	string	Name of the signal.

Example:

Code Block

language	py

simulator.addWave(‘*’)
or
simulator.addWave(‘A’)

...

This method is used to add several signals which will be displayed in vsim.

Arguments:

Name	Type	Description
waveList	list	List of signal.

Example:

Code Block

language	py

simulator.addWaves([‘A’, ‘B’, ‘O’])

...

If a simulation is launched when the project is on its native state, the source files must have been added to the project in the right compile order. Otherwise the simulation will fail.

Arguments:

Name	Type	Description
graphical	boolean	Specify if the vsim GUI should be launched or not.

Example:

Code Block

language	py

project = createProject()
project.load(‘routed.nym’)
simulator = project.createSimulator()
simulator.setTestBenchTop(‘testbench’)
simulator.addTestBench(‘testbench.vhd’)
simulator.launch(True)

...

This method is used to set length in time of the simulation. If not specified (or set to ‘’), vsim will be launched with run -all.

Arguments:

Name	Type	Description
duration	string	Duration of the simulation.

Example:

Code Block

language	py

simulator.setDuration(‘250ns’)

...

This method is used to set the top cell name of the testbench.

Arguments:

Name	Type	Description
testBenchTop	string	Top cell of the testbench.

Example:

Code Block

language	py

simulator.setTestBenchTop(‘testbench’)

...

This method is used to set the working directory of the simulation

Arguments:

Name	Type	Description
workingDirectory	string	Working directory, relative to the project directory.

Example:

Code Block

language	py

simulator.setWorkingDirectory(‘simulation’)

...

This argument method is used to get the clock from a given clock name. A valid clock should be a clock created by command createClock.

Arguments:

Name	Type	Description
clock_name	string	the name of the clock used to get the valid clock.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.setClockGroup(getClock('clk1'), getClock('clk2'), 'exclusive')

...

This argument method is used to get the net from a given clock net name. It is used by createClock method to specify a clock related point as argument.

Arguments:

Name	Type	Description
clock_net_name	string	the name of the net clock. The path must be set entirely.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)

...

This argument method is used to get the clocks from a given clock name expression. A valid clock should be a clock created by command createClock.

Arguments:

Name	Type	Description
clock_name_expression	string	the name expression of the clock used to get the list of clocks.

Example:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLOCK[1]'), 'clk1', 2700)
project.createClock(getClockNet('CLOCK[2]'), 'clk2', 5000, 0, 2000)
project.createClock(getClockNet('CLOCK[3]'), 'test_clkA', 5000, 0, 2000)
project.createClock(getClockNet('CLOCK[4]'), 'test_clkB', 5000, 0, 2000)
project.setClockGroup(getClocks('clk*'), getClocks('test_clk*'), 'exclusive')
project.setClockGroup(getClocks('clk[1-2]'), getClocks('test_clk`[AB]`'), 'exclusive')

...

This argument method is used to get the instances from an instance name. It can be used by some nxpython methods (addMappingDirective, addMemoryInitialization).

Arguments:

Name	Type	Description
instance_name	string	the name of the instance used to get the valid instance. All regular expressions are allowed and special characters must be escaped.

Example:

Code Block

language	py

project = createProject()
project.addMappingDirective(getInstances('smul_4|mult_S'), 'MUL', 'DSP')

...

This argument method is used to get the models from a model name. It can be used by some nxpython methods (addMappingDirective, addMemoryInitialization).

Arguments:

Name	Type	Description
model_name	string	the name of the model used to get the valid model. All regular expressions are allowed and special characters must be escaped.

Example:

Code Block

language	py

project = createProject()
project.addMappingDirective(getModels('myTest_myFifo'), 'RAM', 'DFF')

...

This argument method is used to get the port from a given port name. Some nxpython methods need a port as argument.

Arguments:

Name	Type	Description
port_name	string	the name of the port used to get the valid port. The path must be set entirely.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setInputDelay(getClock('CLK'), 'rise', 1000, 1500, getPort('RST'))

...

This argument method is used to get the ports from a given port name expression. Some nxpython methods need a list of ports as argument.

Arguments:

Name	Type	Description
port_name_expression	string	the name expression of the port used to get the list of ports.

Example:

Code Block

breakoutMode	wide
language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'CLK', 8000)
project.setOutputDelay(getClock('CLK'), 'rise', 1000, 1500, getPorts('dataout[`[0−5]`]'))

...

This argument method is used to get the register from a given register name. Some nxpython methods need a register as argument.

Arguments:

Name	Type	Description
register_name	string	the name of the register used to get the valid register. The path must be set entirely.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegister('UUT1|Gen_seq[3].seq_i|temp_reg[1]'),
		              getRegister('UUT2|dout_reg[61]'))

...

This argument method is used to get the register clock from a given register name. Some nxpython methods need a clock as argument.

Arguments:

Name	Type	Description
register_name	string	the name of the register used to get the valid clock.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getRegisterClock('reg1'), 'clk', 10000)

...

This argument method is used to get the registers from a given register name expression. Some nxpython methods need a list of registers as argument.

Arguments:

Name	Type	Description
register_name_expression	string	the name expression of the register used to get the list of registers. All regular expressions are allowed and special characters must be escaped.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.addFalsePath(getRegisters('UUT1|Gen_seq[3].seq_i|temp_reg[`[0-9]`]'),
		               getRegister('UUT2|dout_reg[61]'))

...

This argument method is used to get all the registers from the same clock domain. Clock must be created before.

Arguments:

Name	Type	Description
clock_name	string	the name of the created clock.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('clk1'),'clk1',20000,0,15000)
project.addFalsePath(getRegistersByClock('clk1'), getRegister('UUT2|dout_reg[61]'))

...

This argument method is used to get the wfg clock from a given wfg name. Some nxpython methods need a clock as argument.

Arguments:

Name	Type	Description
wfg_name	string	the name of the wfg used to get the valid clock.

Example:

Code Block

language	py

project = createProject()
project.load('routed.nym')
project.createClock(getClockNet('CLK'), 'clk', 8000, 0, 4000)
project.developCKGs()
project.createGeneratedClock(getWFGOutput('wfg_clk[1]'), getRegister('data_reg[0]'), 'clk1_div2', 				                 
                             {'DivideBy': 2})

...

The following table shows the revision history of the Impulse_NXpython specification document:

Date	Version	Revision
2022-12-15	1.0.1	Initial draft datasheet.

Versions Compared

Old Version 7

New Version 8

Key

General commands

change_project_dir

log_directory

exportPlacement()

exportRegions()

importPlacement([filename], [regions], [modules], [importAll])

initRegister(command, value)