...
It is recommended to rather use python method addMemoryInitialization described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification as it is compliant with inferred and instantiated memories.
...
In order to get complexity module by module without confining it in a region, it is possible to use addModule method described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification.
Refer to #Floor_planning_Complexity for more details.
...
Please refer to createClock and createGeneratedClock described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification .
If a PLL is used, PLL output clock frequencies are automatically computed by the software.
...
Please refer to addFalsePath and addMultiCyclePath in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification .
Clock groups can be created if clock domains are completely unrelated.
...
It is possible to map this operators in LUT, Carry or DSP thanks to addMappingDirective method described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification .
By default, adders are mapped into Carry and Multipliers in DSP. But it can sometimes be interesting to change default mapping directives.
...
Memories can be mapped into logic elements (LUT/DFF), register files (RF), Memory Blocks (RAM) or Memory Blocks protected by EDAC correction thanks to addMappingDirective method described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification .
By default, small memories (equal or less than 64x16) will be mapped into RF and bigger mapped into RAM. But it can sometimes be interesting to change default mapping directives.
...
Define a floor plan for the design depending on module relationships and pinout.
Apply the floor plan to your NXmap project using confineModule described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification . Check #Floor_planning_Constrain_module for information about constraint setting.
If needed, repeat this process going deeper and deeper in the design hierarchy.
For last most critical paths, use constrainPath described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification in order to create a region with only a few elements contained into the specified path. Check #Floor_planning_Constrain_path_between_registers for information about constraint setting.
It can also have a very positive impact to create unitary projects and reuse the routed projects as a blackbox in your final top project using addBlackBox described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification .
It is also possible to place manually instances in a specified spot thanks to the following NXpython methods all described in /wiki/spaces/~814749387/pages/48660481 Impulse 23.1 NxPython Specification :
addPLLLocation for PLL instance in a CKG. Check #Instance_placing_Ring_placing for information about constraint setting.
addWFGLocation for WFG instance in a CKG and a WFG spot. Check #Instance_placing_Ring_placing for information about constraint setting.
addRAMLocation for RAM instance in a CGB. Check #Instance_placing_Ram_placing for information about constraint setting.
addDSPLocation for DSP instance in a CGB and a DSP spot. Check #Instance_placing_Dsp_placing for information about constraint setting.
setSite for LUT/DFF/CY in a TILE. Check #Instance_placing_Tile_placing for information about constraint setting.
...